Calculator Lab Exercises

1. Calculator Lab Exercises Bruce Wile, IBM Design Automation Conference Sunday, June 9, 2002

2. Calc Resources • Web site contains: • Design source (VHDL and Verilog*) • Design Specifications • Bug lists and bug disables • *Verilog has minimal usage and may contain other bugs

3. Calc Lab Overview • Series of 3 lab exercises • Each grows in complexity and builds upon previous design • “Built-in” bugs give active verification experience • Labs were created by IBM for the purpose of verification education • Used internal to IBM and at Universities • Calc1 in 1994; Calc2 & Calc3 in 2000

4. Calc1 Function • Calculator has 4 functions: • Add • Subtract • Shift left • Shift right • Calculator can handle 4 requests in parallel • All 4 requestors use separate input signals • All requestors have equal priority

5. Calc1 I/O c_clk req1_cmd_in<0:3> out_resp1<0:1> req1_data_in<0:31> out_data1<0:31> calc_top (Design Under Test) req2_cmd_in<0:3> out_resp2<0:1> req2_data_in<0:31> out_data2<0:31> req3_cmd_in<0:3> out_resp3<0:1> req3_data_in<0:31> out_data3<0:31> req4_cmd_in<0:3> out_resp4<0:1> req4_data_in<0:31> out_data4<0:31> reset<0:7>

6. Calc1 Port Timing

7. Calc1 Sample Bugs • Adder (bit 18) gives wrong answer • Must exercise all bits in adder • Overflow not detected • Must try edge conditions

8. Calc2 Function • Same commands as Calc1 • Each port can now have up to 4 outstanding commands in the system • Up to 16 total commands • Out-of-order response may occur • Depends on backlog in adder and shifter • Requires 2 bit “tag” identifier for each port

9. req1_cmd_in req1_data_in req1_tag_in req_resp1 req_data1 req_tag1 Calc2 Port Timings

10. Calc2 Sample Bugs • Add and shift commands from same port collide at output • Window condition on shared resource • Shift command gets lost • Buffer overrun • “Garbage” on the tag bus when not in use • All outputs must be monitored all the time

11. Calc3 Function • Design now has 16 internal data registers • Arithmetic operands no longer sent by requestor • Operand data is read internally from registers • Two new commands added to access registers • Fetch from register x; Store to register x • Two new branch commands • Successful branch causes next command from port to be skipped • Each requester can still send in up to 4 commands • 2 bit tag on request • Using same tag simultaneously is not supported

12. Calc3 Function (Pg 2) • Each port requestor is sending an instruction stream • Data doesn’t accompany command anymore • Example: Commands from Port 1: ADD R1, R2 R3 SHL R3, R4 R5 • All ordering rules are in the spec.

13. Calc3 High Level Diagram Array write and Adder cmd_in1 resp1 output ALU Input stage Stage Priority cmd_in2 resp2 Registers Dispatch Access cmd_in3 resp3 ALU Input Array write Stage Shifter and output stage cmd_in4 resp4 Flow

14. Calc3 Sample Bugs • Priority simultaneously dispatches an add and shift command that both write to the same register • Window conditions in control logic causes data collision • Branch follower writes results to register even when command should be skipped • Specification not followed • External response correct, but internal data corruption

15. Lab Exercise Notes • Use specifications strategically • Give students enough of the spec to get started…but not necessarily the whole spec • Require a testplan for calc2 and 3 • Testplans evoke spec clarifications • New lab exercises encouraged!