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FEE Electronics progress

FEE Electronics progress. PCB layout. Layout current. Memory Target 400MHz data transfers 200MHz clocks. Memory routing rules :- Data byte lanes and clocks routed to within 0.5mm Address and control bus routed using a tree structure with all branches equal in length

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FEE Electronics progress

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  1. FEE Electronics progress PCB layout

  2. Layout current • Memory Target • 400MHz data transfers • 200MHz clocks • Memory routing rules :- • Data byte lanes and clocks routed to within 0.5mm • Address and control bus routed using a tree structure with all branches equal in length • Terminate data byte lanes both series and parallel. • Terminate address and control bus to balance across all devices.

  3. Layout to do • Complete memory • Gbit Ethernet. • ADC output signals to the FPGA. • Discriminator signal connections to the FPGA • Mezzanine connector signal definition • Clock distribution to the ADCs • Power supply blocks and delivery planes. • FPGA configuration memory. • Temperature sensors, RS232, LEDs etc.

  4. Problems • Patrick on leave from April 3rd to 20th • AGATA week in Cologne March 30th to April 1st . • Pcb data needed at manufacturers by 9th March • Revised bill of materials (BOM) needed by assembler as soon as possible. • Too many interruptions !

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