Progress of STS FEE development

1. Progressof STS FEE development E. Atkin (MEPhI), A. Voronin (MSU) CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

2. Outline • 8 channel CSA chip (2005 run) has been developed and mostly tested • Analog derandomizer chip (prototype 1, 4*2) has been designed and manufactured in April 2006 run. It should be tested this year • Design of analog derandomizer chip (prototype 2) has been started • ADC building blocks have been designed and manufactured in April 2006 run. The results of further simulations of whole ADC are given ( talk of A. Simakov) • Multipurpose test station for chips is designed and under manufacture now • Interconnection prototypes have been developed and are tested CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

3. CBM CSA prototype chip UMC 0.18um CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

4. Specifications • Dynamic range of a few MIPs; • Min signal (1MIP at 100 µm thick) – 7000 electrons per MIP; • Signal-to-noise ratio better than 10 for 1 MIP; • Detector (sensor) capacitance in the range 30-100 pF; • Max capacitive load – 100 fF (on-chip load); • Low power consumption of about 1 mW/channel; • Rise time (CSA output) – 10-200 ns; • Number of channels – 8; CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

5. Specs II • Detector coupling: a) AC – capacitor is on the detector or b) DC – CSA built-in leakage current compensationIt should be possible to read-out Si-strip signals in both AC- and DC- coupling modes without saturation. CSA should withstand a maximum sensor leakage (dark) current as high as 1 μA; • Supply voltages – (+1.8V typ.); • Minimal number of external components; • Technological process: the 0.18 µm CMOS one from UMC, Taiwan (6 metals, 1 poly) with MMC and RF options provided CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

6. CSA structure CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

7. CSA inside Schematics, layout and package CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

8. Chip manufacture and packaging • Multi-multi PW run for CBM provided via Europractice foundation was used for the chip manufacturing • For performing the lab tests there was used a set of 5 CSA chips, packaged in CLCC68 case. The corresponding bonding diagram is shown on the next slide CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

9. Bonding diagram used for CLCC68 case CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

10. Support board features • Adjustable voltage regulators 0.9V and 3.3V • Calibration capacitors • Commutation of detector capacitor equivalents • Low input capacitance line driver (CIN ~ 2 pF) • Voltage and current bias components • Offset regulators • Commutation of output loads • Low level clock drivers • All components are installed into sockets CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

11. Support board (drawing and photo) CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

12. CSA DC tests Power consumption of separate channel does not exceed 1.3 mW (Table 1). A channel to channel variation of input and output potentials for the CSA is presented in the table 2. Table 2 CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg Table 1

13. CSA response (simulation) Rising and falling edges at small input signal (different time scales) CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

14. CSA response (scope waveforms) CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

15. Leakage current compensation Leakage current compensation (simulation) Leakage current compensation (lab tests) CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

16. Cdet = 0 pF 100 pF positive charge negative charge Study of the CSA dynamic range Noise level 450 uV (350uV simulated) CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

17. Derandomizer chip (prototype1) CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

18. Layout view CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

19. Multipurpose test station Biases, References, Voltage regulators USB Multichannel ADC with USB and control bus Fast S&H CHIP Picoprobes Control FPGA Application Specific Board MUX DAC CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

20. Multipurpose test station set for unpackaged chips CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

21. Interconnection prototypes CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

22. Thus … • 8 channel CSA chip has been developed and tested. • Analog derandomizer chip (prototype 1) has been manufactured. • Design of analog derandomizer chip (prototype 2) has been started. • ADC building blocks have been designed and manufactured. Development of ADC is in the progress. • Multipurpose test station for chips is under manufacture. • Interconnection prototypes have been developed. CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

23. Outlooks • Participation in creation of joint CBM mixed-signal block library • Development of self-triggered FEE ASICs (FP7?) • Progressing of the interconnection detector-FEE • Development of test technique, including rad hard ones CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg

24. Hoping on collaboration with other teams.. Thanks for your attention! CBM collaboration meeting, 20-22 Sept. 2006, Strasbourg