Preliminary thoughts on SVT electronic design

1. Preliminary thoughts on SVT electronic design Giuliana Rizzo INFN and University, Pisa SuperB Detector R&D Workshop SLAC February 14-16 2008 Electronics Session - February 14. 2008

2. Layer0 Pixel sensor + front-end chips 20 cm HDI Si Wafers HDI Power/Signal Power/Signal Data Data Front-end chips 30 cm 40 cm SuperB SVT LayerRadius 0 1.5 cm 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 5 11.4 to 14.6 cm • Baseline: use an SVT similar to the BaBar one adding a Layer 0 • Layer 0 options: striplets or thin pixels. • Each layer has several modules, mechanically independent units (52+8) • Each module has 2 half-modules, electrically independent units: • Sensor, front-end chips, HDI with power/signal input and data output link Strip(lets) half-module Pixel half-module Electronics Session - February 14. 2008

3. Power Supplies Back Cables MUX Power Front Cables HDI Link Matching Card Si Wafers HDI Kapton Tail DAQ Link Fiber Optic to DAQ BaBar SVT Data Transmission HDI: High Density Interconnect. Mounting fixture and cooling for readout ICs. Kapton Tail: Flexible multi-layer circuit. Power, clock, commands, and data. Matching Card: Connects dissimilar cables. Impedance matching. HDI Link: Reference signals to HDI digital common. DAQ Link: Multiplex control, demultiplex data. Electrical -- optical conversion. The BaBar SVT consists of • ~150K channels • 1188 chips • 104 half-modules, or 104 HDIs • Double sided • 208 readout sections (ROS) • 52 HDI-Link cards • 28 DAQ-Link cards • 14 ROMs On Detetctor Off Detetctor Electronics Session - February 14. 2008

4. Front-end chips for SuperB • Front-end chips: • amplify, shape, digitize sensor signals. • Perform timestamp association • Sparsified readout • High background rate expected at Layer 0 (~5 MHz/cm2) imposes very fast readout. • Striplets readout: existent chip FSSR2(BteV) good candidate: • Readout efficiency not an issue with background rate x 10  6% occupancy in 132 ns time window • Data-driven architecture • 2 main clocks: RDclock 70 MHz, BCclock for timestamp ~100 ns • Could be used also for Layer1-5 • Details in V.Re’s talk at the SVT parallel • MAPS sensor/readout: data-driven readout architecture under development: sparsification and timestampinformation implemented in CMOS MAPS matrix. • APSEL4D 4k pixels in production • APSEL256x256 66k pixels needed for Layer 0 multichip modules • To cope with background rate x 20 full matrix needs RDclock 160 MHz,, BCclock for timestamp ~100 ns • Details in A.Gabrielli’s talk at the SVT parallel Electronics Session - February 14. 2008

5. Data Driven chips FSSR2: only minor modifications needed for SuperB MAPS: data driven doesn’t need local pipeline for storage in the pixel cell…which is not possible with this technology Could allow to use SVT data for LV1 trigger Test Beam in Sept. 08 with MAPS- striplets module, readout by FSSR2, connected to Associative memory system for track trigger Need very fast link to serialize all data from HDI to DAQ (see next tables) Triggered chips Sending off chip only data from LV1 evt reduces by ~ 1/10 the load to the data transmission: Assuming 1 us time window read out with 100 KHz LV1 rate Need to investigate if there is a good match for striplets! MAPS readout: need to implement pipeline for storage on chip, outside pixel sensor matrix, increasing the dead area. This readout architecture need to be evaluated. Data driven vs triggered front-end chips Alternative solution (?): • use data driven front-end • add in the HDI custom chip/FPGA to store half-module data during the trigger latency (~12 us) • send out to DAQ only LV1 triggered data to reduce by 1/10 data link speed Pixel sensor + front-end chips Off Detetctor HDI Power/Signal DAQ Fast link Data HDI Power/Signal On Detetctor DAQ Electronics Session - February 14. 2008 link Data

6. SVT in numbers • 6 layers: Layer0 + 5 layers like present BaBar SVT Electronics Session - February 14. 2008

7. Requirements on link speed reduced by 1/10 Assuming 1 us window and 100 KHz LV1 rate Load to the data transmission Simulated Background track rate Present BaBar data Similar in SuperB L1-L5 BaBar SVT evt size L1-L5 ~ 9 kByte Electronics Session - February 14. 2008

8. Requirements on link speed reduced by 1/10 Assuming 1 us window and 100 KHz LV1 rate Load to the data transmission Simulated Background rate x20 (cluster multiplicity and safety factor) Present BaBar data Similar in SuperB L1-L5 Electronics Session - February 14. 2008

9. Conclusions • Present focus of the SVT R&D on Layer 0 technology and front-end. • Choice of the readout architecture for SVT (data push vs triggered) will be done for the TDR. • Background rate in Layer 0 has great impact on the load of the data link. • Need to evaluate all the implications on data transmission and DAQ. Electronics Session - February 14. 2008

10. backup Electronics Session - February 14. 2008

11. The SVT consists of • ~150000 channels • 1188 chips • 208 readout sections • 104 half-modules, or 104 HDIs • 52 HDI-Link cards • 28 DAQ-Link cards • 14 ROMs Electronics Session - February 14. 2008

12. Fast Readout Architecture for MAPS • Data-driven readout architecture with sparsification and timestamp information under development. • In the active sensor area we need to minimize: • the logical blocks with PMOS to minimize the competitive nwell area and preserve the collection efficiency of the DNW sensor. • digital lines for point to point connections to allow scalability of the architecture with matrix dimensions and to reduce cross talk with the sensor underneath. MP 4x4 pixels Matrix subdivided in MacroPixel (MP=4x4) with point to point connection to the periphery readout logic: • Register hit MP & store timestamp • Enable MP readout • Receive, sparsify, format data to output bus Data lines in common 2 MP private lines Column enable lines in common Periphery readout logic APSEL3D: 256 pixels under test APSEL4D: 4k pixels Sub. Nov. 2007 Data out bus Electronics Session - February 14. 2008 50x50 um pitch