Fast A/D sampler characterization presentation

1. 07/04/2011 Performed By: Tal Goihman & Irit Kaufman Instructor: MonyOrbach Bi-semesterial Spring 2011 Fast A/D sampler characterization presentation

2. Introduction • Goal: implement a fast A/D sampler up to 5Gsps. • Input options: • Single channel @ 5Gsps • Dual channel @ 2.5Gsps • Quad channel @ 1.25Gsps • Output - Sampled data available on: • ML605 On-board DDR3 • PC Memory & file system - through PCI-E

3. Hardware Components

4. Simplified Block Diagram Semester A Semester B

5. A/D Sampler The FMC125 is a Quad-Channel ADC that provides four 8-bit ADC channels enabling simultaneous sampling of 1, 2, or 4 channels @ 5 , 2.5 , 1.25Gsps respectively. • Controlled via SPI. • Uses the EV8AQ160 chip from e2v • Features: • Selectable analog input range (500mVpp / 625mVpp) • Selectable input bandwidth (0.5 , 0.6 , 1.5 , 2 GHz) • Individual Gain,Offset & Phase controls • > 60dB channel isolation

6. Memory Controller & Memory • Standard Xilinx MIG implementation for DDR3 Memory Controller. • Performance (on ML605) • 800 MT/s • 64-bit wide interface • = 6.25 GB/s theoretical throughput • ML605 comes with a 512MB DDR3 SODIMM, Expandable up to a 2GB module

7. PCI-Express Block • Xilinx IP available • ML605 can be connected to a PC using PCI-E as: • 8 lane PCI-E Gen1 (250MB/sec/lane) • 4 lane PCI-E Gen2 (500MB/sec/lane) • Both operate at maximum 2GB/s total • Implemented at Part 2 of the project.

8. PC software Block • Read sampled data from PCI-E to memory and disk. • Control Sampling Start / Stop. • Control some system parameters • Configuration of A/D channels • Sample rate • Sampled data size • … • Implemented at Part 2 of the project.

9. Sampling process

10. Timeline

11. Questions?Thanks

12. Backup • Documantaion