1 / 7

Update on Bump Bonding

Update on Bump Bonding. Phone meeting with VTT. 6/8/2008 (Michael, Petra) Prepared a set of questions as collected before (Flavio, Jan, Pierre, …) Mainly concerning sensor design. Sensor Edge Design. How far from the active pixel cell can the dicing lane be placed

wells
Download Presentation

Update on Bump Bonding

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Update on Bump Bonding

  2. Phone meeting with VTT • 6/8/2008 (Michael, Petra) • Prepared a set of questions as collected before (Flavio, Jan, Pierre, …) • Mainly concerning sensor design

  3. Sensor Edge Design • How far from the active pixel cell can the dicing lane be placed • Question needs to be re-discussed with FBK (depends on wafer doping, etc.) • VTT recommendation: at least 560 µm between last active pixel and centre ofdicing lane ; reserve 100 µm between sensors for dicing;

  4. Arrangement of Structures on the Sensor Wafer • VTT recommendation: place prototype chips such that they do not interfere with large sensor dicing; do not place metal on dicing lanes; minimize the number of cuts; wafer large sensor 5 x 2 chips

  5. Placement of Chips on Final Sensor • How big should the distance between diced chip edges be? • Is the “dynamic bump position” on the sensor a problem? • What should be the minimum distance of the bump wrt the active edge of the cell on the sensor? • VTT recommendation: leave at least 100 um between chip edges; “dynamic bump position” poses no problem; Keep at least 30 µm between the pixel metallisation edge and the bump pad center;

  6. Bump Pad Size • Assuming an octagonal pad (ALICE, Medipix, …) what is the preferred bump pad size and bump size. • Taking into account that the MOSIS run will have a 3-5 µm polyimide passivation. • VTT recommendation: preferred passivation opening: 20 µm, bump diameter: 30 µm.

  7. Bump Transfer • Method proposed for prototype chips • Protection of the wire bonding pads during the UMB (under bump metallisation) and wettable metal deposition still needs to be worked out in detail. • Further discussions with VTT needed

More Related