CLUster TIMing Electronics Part II

1. CLUster TIMing ElectronicsPart II Luigi Cappelli on behalf of CLUTIM group SuperB Workshop - LNF – 4 April 2011

2. Outline ADC output signal CLUTIM aims Device Selection (Virtex 5 vs 6) Virtex 6 Layout ISE Development Enviroment VHDL Algorithm FFT Test Future Planning SuperB Workshop - LNF – 4 April 2011

3. ADC output signal 12 bit (6+6) discretized signal 500 MHz frequency LVDS bus • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans SuperB Workshop - LNF – 4 April 2011

4. CLUsterTIMing aims MAX Read & Store Data coming from ADC: Peak Detection Amplitude and Timing Peak Information Storage • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans AMPL ∆T SuperB Workshop - LNF – 4 April 2011

5. Device Selection Virtex 6 ML605 Evaluation Kit FMC Connector • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans SuperB Workshop - LNF – 4 April 2011

6. ML605 Evaluation Kit • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans • VITA 57.1 FMC LPC Connector • Up to 700 MHz • No coupling problems SuperB Workshop - LNF – 4 April 2011

7. VITA 57.1 FMC LPC Connector • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans • 12 differential inputs • 1 differential clock input SuperB Workshop - LNF – 4 April 2011

8. Possible Setup • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans • Possible direct coupling • Using a daughter board • Gandalf Experiment SuperB Workshop - LNF – 4 April 2011

9. Developing Setup FMC • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans BSH • Use of a daughter board to connect ADC to Virtex 6 • Use of another daughter board to connect ADC to Logical Analyzer SuperB Workshop - LNF – 4 April 2011

10. Possible Setup – Daughter Board VITA FMC Connector • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans BSH Connector • Use of a daughter board to connect ADC to Virtex 6 • Impedance Matching SuperB Workshop - LNF – 4 April 2011

11. ISE Development Enviroment • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans • Version 12.4 • HDL-Based Design • Behavioral Simulation • Timing Simulation • Constraints SuperB Workshop - LNF – 4 April 2011

12. VHDL Algorithm Overview • ADC Signal 2 or 3 points average • Smoothing • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans 2° derivative AND Sign • Derivative & Sign Condition Max values storage in memory • Max Detection • Time Counter Enable Signal • Time Window End End Counter Flag SuperB Workshop - LNF – 4 April 2011

13. VHDL Algorithm – Behavioral Simulation ADC Smoothing Enable Max Reg Counter • Smoothing tuning • Enable counter • Max Register • End counter SuperB Workshop - LNF – 4 April 2011

14. VHDL Algorithm – Counter • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans • Triggered by Enable signal • It gives peak timing information SuperB Workshop - LNF – 4 April 2011

15. VHDL Algorithm – Timeout • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans • It gives the end of the event • It is reset by rst_tout signal that is set when a peak is found • End_counter flag SuperB Workshop - LNF – 4 April 2011

16. FFT Check Algorithm • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans • FFT with input signal frequency 500 MHz • ADC Output Signal vs Virtex 6 Input Signal • Find potential signal distortions SuperB Workshop - LNF – 4 April 2011

17. State of the art • III Version of ADC chip developed • VHDL code improvement in progress • Timing Simulation • Constraints • FFT Readout algorithm in progress • Daughter boards layout ready, waiting for realization • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans SuperB Workshop - LNF – 4 April 2011

18. Future planning... • Once the entire chain (ADC + Virtex) will be tested and the VHDL code will be optimized we think to realize a VME board in order to read up to 4 ADC channels. • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans SuperB Workshop - LNF – 4 April 2011

19. Thank you for your attention SuperB Workshop - LNF – 4 April 2011

20. Backup Slides • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans SuperB Workshop - LNF – 4 April 2011

21. Abstract • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans A Cluster Timing Algorithm has been developed in order to store information coming from the 500 MHz ADC signal. In particular the algorithm detect signal peaks, storing their amplitude and timing information. A Xilinx ML605 Evaluation Board has been used in order to develop and test the VHDL code, using a FPGA Virtex 6 chip. The final goal is to develop a VME board in order to read up to 4 ADC channels. Code improvements are currently being evaluated. SuperB Workshop - LNF – 4 April 2011

22. Il BUS di espansione Dip. di Fisica SuperB Workshop - LNF – 4 April 2011

23. SuperB Workshop - LNF – 4 April 2011

24. Device Selection Virtex 5 initially selected ML50X Family • ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans SuperB Workshop - LNF – 4 April 2011

25. ADC output • CLUTIM aims • Device Sel. • Virtex 6 • ISE 12.4 • VHDL code • FFT Test • Future Plans • Previous experimental experiences led to different solution • Pins coupling problems • ( Frequency limitation due to parasitic capacitance ) SuperB Workshop - LNF – 4 April 2011