1 / 56

Testing Combinational Logic: Definitions, Algorithms, and Fault Detection

This article discusses the definitions and concepts related to testing combinational logic circuits, including test generation algorithms, justification and propagation processes, as well as fault detection methods.

wricketts
Download Presentation

Testing Combinational Logic: Definitions, Algorithms, and Fault Detection

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CPE/EE 428, CPE 528 Testing Combinational Logic (4) Department of Electrical and Computer Engineering University of Alabama in Huntsville

  2. Definitions • Test generation algorithms work in terms of: • Primary inputs— (PI) a controllable input to a circuit. E.g., a pin on an IC, or an output of an FF in a scan system • Primary outputs— (PO) an observable output of the circuit. E.g., a pin on an IC, or a D input to an FF in a scan system • Justify, justification— the process of selecting PIs to force a certain line to have a specific value • Propagate, propagation— the process of selecting appropriate PIs that allow a discrepancy “D” to be pushed to a PO • Test generation algorithms are all about • finding the appropriate PIs to control to activate a fault • finding the appropriate PIs to control to propagate the fault to one of the POs. VLSI Design II: VHDL

  3. More Definitions • Forward implication • Def:Knowing one or more gate inputs, imply the output value. • Assume all gate inputs are the same value — either all c or all c’ • Then the output is output = value  i • We can refine this if we know the controlling value • i.e. only one of the inputs needs to have c to know output • Backward implication • Def:Knowing the output and possibly some inputs, imply one or more of the inputs • Assume all gate inputs are the same — either all c or c’ • Then the inputs are: inputs = output  i • We can refine this if we know the controlling value • If the input needed to produce the output is c, then only one input needs to have it. VLSI Design II: VHDL

  4. x 1 0 l 0 1 1 l Justify Algorithm • Justify (l , v) — Recursive algorithm to justify line l to value v l = v if l is a primary input return — you’re done on this path set c and i to controlling/inversion values of gate driving l inval = v  i if (inval == c) select one input j of gate l Justify (j, inval) else for every input j of gate l Justify (j, inval) VLSI Design II: VHDL

  5. justify a to 1 a B PO An example of justification l = v if l is a primary input return — you’re done on this path set c and i to controlling/inversion values of gate driving l inval = v  i if (inval == c) select one input j of gate l Justify (j, inval) else for every input j of gate l Justify (j, inval) VLSI Design II: VHDL

  6. l k Justify enabling values onto other inputs Propagate further Test Generation: Propagate Algorithm • Prop (l , err) — Propagate value err from line l l = err if line l is a primary output return — you’re home k = fanout gate of line l c,i = controlling/inversion value of gate k for every input j of k other than l Justify (j, c’) Propagate (k, err  i) VLSI Design II: VHDL

  7. Testing Digital Circuits • What you know • Fault models — what can go wrong and how we model it • physical and logical • Basic idea of detection — activate fault and propagate to output • What you don’t know • how to figure out, systematically, whether the whole thing works • how to reduce the number of faults to consider when generating tests • Today • Review equivalence and fault collapsing • Begin test generation algorithms VLSI Design II: VHDL

  8. Detection • Basic approach seen so far • Select a line and a fault — line l s-a-v • Activate the fault • Drive line l to v’ — selecting the inputs needed to set an internal line to a known value is known as line justification • Activation creates a discrepancy “D” • Propagate the fault • Propagate the discrepancy D along a sensitized path to any primary output discrepancy s-a-0 0 1/0 Notation: good value/bad value x 0/1 1 VLSI Design II: VHDL

  9. Fault Dominance • Equivalence vs. Dominance • Dominance is a special case of fault equivalence • Fault equivalence, if Z f (x) = Z g (x) for all xthen the faults are functionally equivalent. • If this is true for a subset of x, then there is a dominance relation • Dominance • Let Tg be the set of all tests that detect a fault g. • A fault f dominates the fault g iff f and g are functionally equivalent under Tg. Z f (t) = Z g (t) for all t in Tg • Tg is a subset of Tf VLSI Design II: VHDL

  10. Equivalence and Dominance Summary • What are the equivalence classes? s-a-0 s-a-1 Equivalence A0, B0, Z1 s-a-0 s-a-1 s-a-0 s-a-1 Dominance Z0 dominates A1, B1 11, 01, 10 VLSI Design II: VHDL

  11. Tg 10 01 00 Tf Aside: Fault Location • Detection got us down to three tests • We’re left with three tests for this gate if we’re interested in fault detection. • If we’re interested in fault location, we need more • To isolate y s-a-1 • Need to apply both 10 and 01 • 10, alone, detects the equivalent faults y s-a-1 and z s-a-0 • 01, alone, detects the equivalent faults x s-a-1 and z s-a-0 • Together, they can isolate the three faults (assuming only one fault active). x sa1 z sa0 y sa1 VLSI Design II: VHDL

  12. define fault model select target fault no more faults: done generate test for target fault simulate discard detected faults Overall process set of faults for circuit VLSI Design II: VHDL

  13. Test Generation • Toward an algorithmic means to generate test vectors • What do we want in a test vector? • fault activation and propagation • if the discrepancy D wiggles (i.e. from good to bad), then so does the output • how do we determine if a function changes with respect to a variable • Use Automatic Test Generation algorithms (ATG) VLSI Design II: VHDL

  14. Primary inputs and outputs • Test generation algorithms work in terms of: • Primary inputs— (PI) a controllable input to a circuit. E.g. A pin on an IC, or an output of an FF in a scan system • Primary outputs— (PO) an observable output of the circuit. E.g. A pin on an IC, or a D input to an FF in a scan system • They all operate in terms of: • finding the appropriate PIs to control to activate a fault • finding the appropriate PIs to control to propagate a discrepancy to one of the POs. VLSI Design II: VHDL

  15. a B PO PIs Propagate, Justify • A few definitions • justify, justification— the process of selecting PIs to force a certain line to have a specific value • the verb … justify a 0 on the input a of gate B • the noun … justification is the process of justifying • propagate, propagation— the process of selecting appropriate PIs that allow a discrepancy “D” to be pushed to a PO • … propagate the D to any output • … propagation is the process • involves justification VLSI Design II: VHDL

  16. Imply all you can… • Forward implication • Def:Knowing one or more gate inputs, imply the output value. • Assume all gate inputs are the same value — either all c or all c’ • Then the output is output = value  i • We can refine this if we know the controlling value • i.e. only one of the inputs needs to have c to know output VLSI Design II: VHDL

  17. Look behind yourself too… • Backward implication • Def:Knowing the output and possibly some inputs, imply one or more of the inputs • Assume all gate inputs are the same — either all c or c’ • Then the inputs are: inputs = output  i • We can refine this if we know the controlling value • If the input needed to produce the output is c, then only one input needs to have it. VLSI Design II: VHDL

  18. x 1 0 l 0 1 1 l Justify Algorithm • Justify (l , v) — Recursive algorithm to justify line l to value v l = v if l is a primary input return — you’re done on this path set c and i to controlling/inversion values of gate driving l inval = v  i if (inval == c) select one input j of gate l Justify (j, inval) else for every input j of gate l Justify (j, inval) VLSI Design II: VHDL

  19. justify a to 1 a B PO An example of justification l = v if l is a primary input return — you’re done on this path set c and i to controlling/inversion values of gate driving l inval = v  i if (inval == c) select one input j of gate l Justify (j, inval) else for every input j of gate l Justify (j, inval) VLSI Design II: VHDL

  20. l k Justify enabling values onto other inputs Propagate further Test Generation: Propagate Algorithm • Prop (l , err) — Propagate value err from line l l = err if line l is a primary output return — you’re home k = fanout gate of line l c,i = controlling/inversion value of gate k for every input j of k other than l Justify (j, c’) Propagate (k, err  i) VLSI Design II: VHDL

  21. x2 x3 x1 Z x5 x4 Will this always work? • Will justify and propagate always work? • Circuits without reconvergent fanout • “select one” and “justify” are each independent of any previous justification • you’re guaranteed that propagation and justify will not interfere VLSI Design II: VHDL

  22. Will require more justification x2 s-a-0 x3 x1 Z x5 x4 Test Generation: Basic Algorithm • Algorithm to test line l s-a-v begin set all values to x (unknown) Justify line l to value v’ if (v == 0) Propagate D on line l else Propagate D’ on line l end VLSI Design II: VHDL

  23. Automatic Test-Pattern Generation (ATPG) • Test U2.ZN for s-a-1 • 1) Activate (excite) fault =>U2.ZN = 0 • 2) Work backward => A = 0 • 3) Work forward (sensitize the path to PO) =>U3.A2 = 1, U5.A2 = 1 • 4) Work backward (justify outputs) =>ABC = 110 VLSI Design II: VHDL

  24. Reconvergent Fanout Fault B s-a-1? Fault U4.A1 s-a-1? We create two sensitized paths that prevent fault from propagating to the PO. The problem can be solved by changing A to 0, but this breaks rules of the ATPG! The PODEM algorithm solves the problem. Signal B branches and then reconverges at logic gate U5. ATPG works. VLSI Design II: VHDL

  25. d G2 G4 a s-a-1 D’ b G1 c G5 G3 e Test Generation — example • With reconvergent fanout • Fanout paths from a gate reconverge at some later gate • Inputs needed for propagation may be inconsistent with ones needed for justification Procedure: justify G1 to 0 —> a=b=c=1 propagate to G4 —> requires G2 = 1 but a=1 makes G2=0 Inconsistency— crash and burn Kaboom! VLSI Design II: VHDL

  26. Procedure: justify G1 to 0 —> a=b=c=1 propagate to G4 —> requires G2 = 1 but a=1 makes G2=0 Inconsistency propagate to G5 —> justify G3 to 1 this works with e=0 d G2 G4 a s-a-1 D’ backtrack b G1 c G5 G3 e Test generation — example, cont’d • Need to backtrack — propagate on other path VLSI Design II: VHDL

  27. State 1 State 1B State 1A win State 1A1 State 1A2 fail fail Backtracking • Backtracking requires that a decision tree be maintained • Each node describes a design’s state • values previously justified on lines • implications, forward and backward • Each arc describes a new decision • justify a line, activate a fault • Need to be able to go back… • to former state VLSI Design II: VHDL

  28. backtrack Maintaining the decision tree Procedure: justify G1 to 0 —> a=b=c=1 propagate to G4 —> requires G2 = 1 but a=1 makes G2=0 Inconsistency propagate to G5 —> justify G3 to 1 this works with e=0 State 1 all x’s justify G1 to 0 State 1A a=b=c=1 Prop. to G5 Prop. to G4 G3 = 1 e = 0 win G2=1, a=1 inconsistency fail State 1A1 State 1A2 Backtrack, G2=1 no longer part of design state. Revert to previous state. VLSI Design II: VHDL

  29. Observations on approach • Enumeration used • justify algorithm was recursive • When gate has controlling value on input, one path selected • may need to backtrack and follow another • eventually, may need to follow all • Propagate algorithm was recursive • When there is a fanout at a propagation point, one path selected toward output • may need to backtrack and follow another • eventually, may need to follow all • The backtracking, again, is due to reconvergent fanouts and previous values justified on them • No solution? — redundant wrt the fault • As it turns out… • The natural state maintenance in recursive programs can keep track of the decision tree VLSI Design II: VHDL

  30. x D’ x x D-frontier More terminology • When propagating a discrepancy • Often, due to fanout, there are several options • Propagate needs to pick one for the sensitized path • D - frontier • The D-frontier is the set of all gates with D or D’ on one or more inputs and an x on its output (no other inputs are controlling) • This is the set from which you select a propagation (sensitization) path VLSI Design II: VHDL

  31. x d 0 0 G2 G4 a 1 s-a-1 D’ b 1 G1 c 1 0 x G5 G3 G3 x e D-Frontier • Back to our example • After the activation of the fault, and forward implication, the D- frontier is … ? • If D-frontier = Ø, then no path to primary output • failure, backtrack • previous justifications have made this path impossible VLSI Design II: VHDL

  32. x 1 x J-frontier 1 J-Frontier • In line justification… • The J-frontier is the set of all gates whose output values are known, but the outputs are not implied (yet) by the inputs • Some inputs may be known, but the current output value is not implied • Similar to D-frontier, but looking backward VLSI Design II: VHDL

  33. x d 0 0 G2 G4 a 1 s-a-1 D’ b 1 G1 c 1 0 x G5 G3 G3 x e J-Frontier • Back to the Example • The fault is activated and forward implication is done • A gate is selected from the D-frontier for propagation • In this case, G5 is the only choice • The J-frontier is then … ? VLSI Design II: VHDL

  34. Implication Revisited • Implication Process • Compute all values uniquely determined by implication • 1, 0, D, D’, x — looking forward and backward • more aggressive than previous implication • maintain the D and J frontier VLSI Design II: VHDL

  35. Backward Implication new implication front implication front After Before <— 1 x <—1 1 x <— 1 x <— 0 <—0 0 1 1 x x 0 <—0 J-frontier = {…} J-frontier = {… , a} a x a x <—1 1 <— 1 x 1 <— 1 1 —> x VLSI Design II: VHDL

  36. Forward Implication After Before 0 0—> 0—> x x x 1 1—> 1—> x 1 1 0 a 0—> 0 0 a J-front={…} J-front={…, a} x x 1—> 0 a 1 J-front={…} 0 a J-front={…, a} <—0 x D D D—> a x a D-front={…, a} D-front={…} 1—> 1 D x a D 0—> D-front={…} D-front={…, a} 0—> 0 VLSI Design II: VHDL

  37. Where are we now? • Pieces of test generation algorithms seen • justify, propagate • problems with reconvergent fanout • need to backtrack — makes for a messier algorithm • need to keep track of state, and what combinations have been tried before. • heuristics to guess at best “next path” to follow • To come • D algorithm • and eventually Podem VLSI Design II: VHDL

  38. Implication Process Revisited • Unique D-drive • If there is only one gate on the D frontier, then implication propagates D through the gate. • It’s the only direction D could propagate after before D D x D’ —> a x <— 1 D-frontier = {a} D-frontier = { } VLSI Design II: VHDL

  39. All Pieces in Place • Pieces • Controlling and inverting values • Fault activation • Justification • Propagation • Forward/backward implication • D and J frontiers • Decision tree maintenance • Discussion of the D algorithm • note that this is a version of the D algorithm • a number of situations have been left open, e.g. • “select an input …”, “select a gate …” • which one? VLSI Design II: VHDL

  40. D-Algorithm • Initialization • set all line values to X • activate the target fault by assigning logic value to that line • 1. Propagate D to PO • 2. Justify all values • Imply_and_check() does only necessary implications,no choices • if D-alg() == SUCCESS then return SUCCESS • else undo assignments and its implications VLSI Design II: VHDL

  41. Test Generation: The D Algorithm Decorate design with all known values. Check for inconsistencies. if (imply_and_check() == FAIL) return FAIL if (error not at primary output) { if (D-frontier == Ø) return FAIL repeat { select an untried gate (G) from D-frontier c = controlling value of G assign c’ to every input of G with value x if (D-Alg() == SUCCESS) return SUCCESS } until all gates from D-frontier tried return FAIL} if (J-frontier == Ø) return SUCCESS select a gate G from the J-frontier c = controlling value of G repeat { select an input (j) of G with value x, assign c to j if (D-Alg() == SUCCESS) return SUCCESS assign c’ to j /* reverse decision*/ } until all inputs of G are specified return FAIL Push D to a primary output Once at primary output, justify all values needed to have D on the primary output VLSI Design II: VHDL

  42. h d’ d i s-a-1 j n e e’ k g a b c l f f’ m A circuit and fault to test VLSI Design II: VHDL

  43. h d’ d i s-a-1 j n e’ e k g a b l f f’ m Tracing through an example 1 all x’s a = 0, b = c = 1 D 0 1 1 Decisions Implications Comments a = 0 Activate the fault h = 1 b = 1 Unique D-drive through g c = 1 (the unique path for D) g = D D-frontier becomes {i,k,m} VLSI Design II: VHDL

  44. h d’ d i s-a-1 j n e’ e k g a b l f f’ m Tracing through an example 1 all x’s 1 0 D’ a = 0, b = c = 1 D 0 1 1 d = 1 Decisions Implications Comments d=1 Propagate through i i = D’ d’ = 0 D-frontier becomes {k, m, n} VLSI Design II: VHDL

  45. h d’ d i s-a-1 j n e’ e k g a b l f f’ m Tracing through an example all x’s 1 1 0 D’ a = 0, b = c = 1 1 D 0 1 D 1 0 1 d = 1 1 1 1 j=k=l=m=1 Bang Decisions Implications Comments j=k=1 Propagate through n l=m=1 n=D e’=0, e=1 k=D’ But k = 1 Contradiction! D-frontier remains {k, m, n} VLSI Design II: VHDL

  46. h d’ d i s-a-1 j n e’ e k g a b l f f’ m Tracing through an example all x’s 1 1 0 D’ a = 0, b = c = 1 1 0 1 D D’ 0 1 d = 1 1 e = 1 j=k=l=m=1 Bang Decisions Implications Comments e = 1 Propagate through k k=D’ e’=0 j=1 D-frontier becomes {m, n} VLSI Design II: VHDL

  47. h d’ d i s-a-1 j n e’ e k g a b l f f’ m Tracing through an example all x’s 1 1 0 D’ a = 0, b = c = 1 1 0 1 D D’ 0 d = 1 1 1 1 0 1 1 e = 1 j=k=l=m=1 Bang Decisions Implications Comments l=m=1 propagate through n n = D f’= 0 f = 1 m = D’ But m = 1, contradiction! D-frontier remains {m, n} l=m=1 Bang VLSI Design II: VHDL

  48. h d’ d i s-a-1 j n e’ e k g a b l f f’ m Tracing through an example all x’s 1 1 0 D’ a = 0, b = c = 1 1 D 0 1 D D’ 0 d = 1 1 1 1 0 1 D’ e = 1 j=k=l=m=1 Bang Decisions Implications Comments f = 1 Propagate through m m = D’ f’ = 0 l = 1 n = D J-frontier is Null l=m=1 Bang f = 1, n = D party! VLSI Design II: VHDL

  49. What about the J-frontier? • In this example, all inputs were easily justified through implication • essentially, d, e, and f were primary inputs • if these were driven by other gates, the earlier inputs might not have been implied. e.g. a a x x <— 0 0 x x J-frontier = {…} J-frontier = {…, a} VLSI Design II: VHDL

  50. What about the J-frontier? • The D-algorithm: • picks a gate from the J-frontier • and then tries to set each input to a controlling value • If that value fails due to imply_and_check, it is inverted and a new input is tried • how does it handle the case where none of the inputs should be controlling? if (J-frontier == Ø) return SUCCESS select a gate G from the J-frontier c = controlling value of G repeat { select an input (j) of G with value x, assign c to j if (D-Alg() == SUCCESS) return SUCCESS assign c’ to j /* reverse decision*/ } until all inputs of G are specified return FAIL exit here if output of gate G is justified, possibly before setting all inputs VLSI Design II: VHDL

More Related