Hrushikesh Chavan Younggyun Cho

1. Structural Fault Tolerance for SOC HrushikeshChavan Younggyun Cho

2. Agenda • Motivation • Introduction • BISER FF & Razor FF • FITO • Implementation • Simulation result • Conclusion • Future work

3. Motivation • Number of transistors increasing • Cramming more components in a single Chip • Device parameters are not as intended by the designer • SoC design more vulnerable to internal and external noise • Important to design a fault tolerant circuit

4. Introduction • Transient Fault • Temporary faults in flip-flop or latch or any memory cell (SEU) • Temporary faults in a combinational circuit (SET)

5. Introduction • Single Event Upset (SEU) • Another name of Soft Error • Changing state • Ionizing radiations • Electromagnetic interference

6. Introduction • Soft Error Fault Tolerant System • Detect and correct the soft errors [Mitra-05]

7. Introduction • How to make the fault tolerant circuits? • Redundancy • Hardware & Time • BISER FF & Razor FF

8. BISER FFs • Built-In Soft Error Resilience • C-element • Four Latches [Ravindran-09]

9. BISER FFs • C-element [http://en.wikipedia.org/wiki/C-element]

10. BISER FFs • C-element with four latches Transparent Transparent 1 0 1 0 1 0 1 0 1 [Ravindran-09]

11. Razor FFs • Razor FF [Ravindran-09]

12. Razor FFs • How to select CLK Delay • The shortest path is more than CLK delay • Time violation can corrupt the system • More buffers on the path can prevent

13. Working of Razor F/F (Fault in Sequential Part) 1 1 0 1 1 1 1 1 0 1 0 1 0 1

14. Working of Razor F/F (Fault in Combinational Part) 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0

15. FITO • Fault Injection Tool • High observability and controllability • A key to evaluating fault-tolerant techniques

16. FITO • Synthesizable bit-flip fault model [Reddy-13]

17. Implementation • Implemented 5 Stage Pipeline to test BISER and Razor flop. • Pipeline implements ADD, ADDI, SUB, AND, OR, SLL, LW, SW, BEQ, JUMP and HLT. • Replaced ID/EX and EX/MEM flops with fault tolerant flops. • Executed 4 test benches to test the system.

18. Pipelined Processor Architecture

19. Tools • Verilog HDL • Synopsis Design Vision

20. Testing Methodology • Clock Period ~ 20ns • Clock Delay ~ 4ns (for Razor F/F) • Transient fault duration < 4ns • Number of faults injected/iteration = 5 • Random duration between two consecutive faults.

21. Circuit Modifications with FITO (BISER)

22. Circuit Modifications with FITO (Razor)

23. Simulation and Results INDIVIDUAL AREA AND POWER

24. Area and Power after 2 Pipelines Swapped with BISER and Razor F/F

25. Performance for Normal Operation

26. Performance with BISER F/F

27. Performance with RAZOR F/F

28. Conclusion • Project implemented two types of fault tolerant design techniques. • Choice of design application specific. • Both techniques efficient and practical to design systems.

29. Future Work • Reduce cost due to latches. • Implement Dynamic Voltage and Frequency Scaling for Razor. • Hybrid Flop • Fault Tolerance for Memories

30. 1 Thank You 

31. 1 Questions?