FVTX Answers May 25th

1. FVTX Answers May 25th • What are the requirements for FVTX, from a performance/physics perspective ? • What are the electronic requirements and can existing chips be used for FVTX ?

2. FNAL Chip Comparison Signal 24000 e for 300 µm Si Sensor, thinning desirable for small material budget

3. Detector Requirements I • How many layers are needed ? • After the first round of simulations we came to the conclusion that we need 4 layers • Need at least 3 points for tracking • Need good efficiency (3 out of 4 points) • This is the current situation • Shaded area 3 or 4 hits • Lines indicate barrel hits

4. Detector Requirements II • What is the expected occupancy ? • Use Central AuAu collision • What is the minimum segmentation required ? • The requirement is that the max occupancy be below 1.5 percent • The combined answer is that Hubert van Hecke did simulations which show that for the inner most ring in central Au+Au one reaches that goal for • 2 mm by 50 micron strips at the inner radius • 11 mm at the outer radius • Simulation has current barrel and endcap • Details next silde

5. Detector Requirements II Hit Density from Central AuAu Collision Assumptions: We want the Occupancy < 1.5% We apply a Looper factor = 2 MC calc occupancy < 0.7% Strip width from studies = 50 µm Implies Inner Strip length = 2 mm Tracks /cm**2 about 6

6. Detector Requirements III • What is the required position resolution and what does this imply for the segmentation and the multiple-scattering (e.g. radiation thickness) of the first layer ? • The position resolution is driven by the decay physics • Separation between neutral and charge D-mesons (single muon) • Separation of J/psi from B-meson decay (secondary vertex) defines resolution requirement • Currently the resolution is radiation length limited • Matches currently available chips m ct GeV mm D0 1865 125 D± 1869 317 B0 5279 464 B± 5279 496

7. Silicon Detector Simulated Performance Endcaps: occupancy: all disk < 1.5 % (ministrips) resolution: zvertex, B→ J/Ψ→ μ+μ- < 200 µm B decay length zvertex distance [mm]

8. Electronics Requirements I • What is the required S/N ? • About 25/1 for a 150 micron detector • We are aiming for a maximum of 500 electrons noise • Keep occupancy due to noise as low as possible ! • MET BY ALL NEW FNAL CHIPS • What is the thermal requirement ? • Original HYTEC study for endcaps was performed for • 1/10 Watt/cm^2 for all silicon area • Reduced material budget • Current specification to keep cooling really simple • 1/10 Watt/cm^2 for the readout chip area !!! • Excludes chips such as SVX and FSSR for they have a factor 10 higher power

9. Electronics Requirements II • Multi-event buffering ? • Current Phenix specification • 5 events with 4 buckets dead time in between, i.e. all 500 ns • Asynchronous Readout speed 600 nsec for central Au+Au • 1 percent Occupancy in central Au+Au (10Khz for RHIC II) • 50 micro-second hit spacing per chip …. • Asynchronous Readout speed for pp is 100 nsec • Large safety margin (full simulation to be started with FNAL)

10. Electronics Requirements III • What about form factor? The maximum occupancy of 1 percent in central Au+Au dictates the 2 mm by 50 micron strip length • This strip length suggests a sensor width of no more than 4 mm at inner radius • Or is this really a criterion, since different geometries might be feasible if we forgo the bump-bonding ? • Yes and No  • We need to solve the bus challenge for PHX • We have 2 million channels (wires ????), • Mix between • Bumps for strips • Wires for bus

11. Electronic Requirements IV • How does a data-push system fit in with phenix-daq, how would this work if there was no endcap lvl1-trigger system initially, then how would it work with a lvl1-trigger, i.e. if the development was staged ? • See next slides

12. Slide from Oct 2004 Fiber 2.5 Gbit/s OASE chip Slow Control ~100 Hz LVDS 6 x 160 MBit Endcap Readout: Front End RISC onboard Hit: 9 bit address ,3 bit adc, 4 bit chip-id, tag 8bit, i.e.24 bits 6 x 512 channels PHX/FPIX2 is zero supressed !!! 5 x 512 channels

13. OASE Chip - University HD • 1st Generation exists • TR work to specs • Receiver has problems • 2nd Generation in October • ‘Will need in January ~2000 for Alice TDR • 3rd Generation next Spring • Will have RISC on it • This RISC was independently prototyped and work • They will provide sizes and power consumption for 1st generation in the next few days

14. Oase Block Diagram

15. Slide from Oct 2004 Endcap Readout: Back End 24 cards each end ! LINUX PCs PHENIX emulator FPGA GLink Event Tag DATA (copy) 4 X (4 wedges) Readout Unit (PCI bus) Fiber 2.5 Gbit/s OASE chip Slow Control ~100 Hz TRACKING FPGA DATA IN FPGA Arcnet • Parallel Path: • PHENIX Standard • Trigger Level I or II output

16. FVTX Usage of the FPGA Board from University Heidelberg PHENIX Emulator Tracking Trigger From OASE Global Level I GLINK Slow Control

17. Programmable Mezzanine Card From FNALnot as powerful but used for initial LANL setup

18. Chain ….. • Silicon Detector • 150 micron mini-strips • Front End Chip • PHX with Data Push • Serializer/Optical Link • Oase from HD • Optical Receiver • Commercial on PCI Board • Receiver Board • Emulates PHENIX Readout Standard • Allows to Study Triggering • This is parallel

19. Summary • Need to do the R&D with FNAL now to get • Chips with 1/10 Watt/cm^2 Power • Data-push for free (all there new chips have it) • Right S/N, threshold performance • The right form factor • Solution for the bus