Low Power and Reliable Design for Emerging Technologies

1. Low Power and Reliable Design for Emerging Technologies Yuanqing Cheng CADET Laboratory School of Microelectronics Beihang University

2. A Big Picture – Post Moore Era Emerging technology [Numerical Technologies] Tech. node scaling challenge Process complexity Technology node

3. New Design Substrates • RRAM • STT-MRAM • Carbon naotube

4. 3D Stacking Technology [micron.com] [Vasilis, UoM] [Tezzaron]

5. Outline • Thermal and PSN aware Design for 3D Integration Circuits • Low Power Design and Reliable Design for STT-MRAM • Low Power Design for Carbon Nanotube SRAM • Conclusions and Prospects

6. What is 3D IC ? • Advantages of 3D • Smaller global timing delay; • Smaller interconnect power consumptions; • Higher integration density (smaller form factor) • Integration of disparate technologies • Challenges of 3D: • Chip yield due to novel fabrication process • Thermal related issues • Higher current density threatening reliability of 3D ICs… Through Silicon Via (TSV) F2B bonding Through Silicon Via (TSV) B2B bonding F2F bonding Through Silicon Via (TSV) C4 bump

7. Signal Integrity & Thermal Challenges • Current density increase • Supply voltage and transistor scaling • Shrinking noise margin • Power supply noise propaga-tion among tiers Power Supply Noise Heat dissipation Supply drop Noise margin Ground bounce Veff Challenge 1. Signal integrity Challenge 2. Thermal dissipation • Non-uniform thermal distributionamong layers • Thermal correlation among layers • Need effective and efficient thermal model [Handbook of 3D Integration]

8. Motivation 3D Homogeneous MPSoC Workloads profiles T1 Thermal Cons. T2 T3 T4 T5 PSN minimization, Performance maximization

9. Power Delivery Network Modeling

10. Capturing PSN Induced Performance Loss • PSN Estimation [Conn, ICCAD] • Timing Variations due to PSN [Martin, ADVP] • Performance Loss (Group 1) (2) (3)

11. Thermal Modelling Methods • 1D thermal model [Kleiner, IEDM] • Duality of thermal and • electrical properties [Daloukas, DATE] • Finite element or boundary element methods • [Ladenheim, ICCAD]

12. Problem Formulation

13. Our Optimization Framework Power trace Generation PDN Stimuli Abstraction Execution performance evaluation

14. Algorithm Work Flow Optimize further utilizing TABOO search No Yes

15. Experimental Results 12% 17% (a) Running tasks on the 2x2x2 MPSoC. PSN comparisons of our proposed task scheduling algorithm and the thermal aware task scheduling algorithm given the same thermal constraint. 14.8% 10.2% (b) Running tasks on the 3x3x3 MPSoC. (a) Running tasks on the 2x2x2 MPSoC. (b) Running tasks on the 3x3x3 MPSoC. PSN comparisons of our proposed task scheduling algorithm and the thermal aware task scheduling algorithm given the same thermal constraint when the core power is doubled

16. Outline • Thermal and PSN aware Design for 3D Integration Circuits • Low Power and Thermal aware Design for STT-MRAM • Low Power Design for Carbon Nanotube SRAM • Conclusions and Prospects

17. Introduction to Spintronics • “Electron does not have only a charge, but also a spin” Is it possible to construct a practical electronic device that operates on the spin of the electron, rather than its charge? Giant MagnetoResistance (GMR) FM: Ferromagnetic NM: Non Magnetic (Metal) A.Fert et al., PRL, 1988 Peter Grünberg Albert Fert [Chappert, Nature Materials]

18. Perpendicular Vs. In-Plane STT-MRAM [Zhang, TED]

19. Leakage Power – Nightmare! Challenges: • HighstaticpowerconsumptionduetotheCMOSleakagecurrent. • HighpowerdensitywhichwillincreasetheworkingtemperatureofCPU [L. Wilson. ITRS]. Fig.1The power dissipation trend of integrated circuits

20. Promising Thermal Properties [Bi, TR] • Thermal Properties • Write Energy/Latency drop dramatically • Read Energy/Latency slight fluctuations Saturation magnetization MTJ volume Boltzmann constant

21. Motivation of thermal aware NUCAdesign • Current migration policy is notsuitable for non-symmetricalSTT-MRAM access and thermaloblivious • NUMAarchitecture • Hot region (light gray in left figure) • Cool region(dark grey in the left figure)

22. Design and Implementation of “Thermosiphon” • Implementation details Boundary bank Access Read Access Ping-pong effect elimination Write Access

23. Experimentsetup • SPICE simulation (Cell) • NVSim (Bank) • Gem5 (System) • Hotspot (Temperature)

24. Experimental Results • Largest improvement: 7% • Hybrid – 1 • TNUCA: 5.8% • Our work: 7% • Hybrid – 2 • TNUCA: 2.5% • Our Work: 3.9%

25. Experimental Results (Cont.) • Save 22.5% write energy on average. • More write operations have been migrated into hot region compared with T-NUCA

26. Outline • Thermal and PSN aware Design for 3D Integration Circuits • Low Power and Thermal aware Design for STT-MRAM • Low Power Design for Carbon Nanotube SRAM • Conclusions and Prospects

27. CNT and CNT-based Devices • Potential Benefits: • No short-channel effect • More aggressive scaling • High speed and low power • Vsat 2-10X faster than Si • Lmfp > 100nm • Vdd ~ 0.2-0.4V vs 0.6-0.8V Si

28. Introduction to FinFET Lg=21 nm HFIN= 32 nm TFIN= 6.5 nm Pitch= 27 nm [ASAP, ASU] The parameters are optimized for a low power high performance SRAM design by “Arizona state predictive PDK @ 7nm technology”

29. SRAMDesignOptimization Guideline Trade-off Powerefficiency Reliability Performance StaticNoiseMargin(SNM): ReadSNM WriteSNM Readlatency Writelatency Staticpower ReadEnergy WriteEnergy ReadEDP WriteEDP • SRAMcellsizedesignstrategy • Cellratio: β=Wn/Wa or NFIN_n/NFIN_a • Pullupratio:σ=Wa/Wp or NFIN_a/NFIN_p • Exploreβ, σ~[1,3]foragoodtrade-offbetween • performance,powerefficiencyandReliability

30. Direct comparisons of SRAM design Except the write SNM, the size-optimized CNFET SRAM cell is much worse than the FinFETcounterpart.

31. P&E,ReliabilityCo-optimization-CNFET ReadSNM Staticpower ReadEDP WriteSNM WriteEDP

32. ComparisonsAfter Optimizations

33. SRAM layout optimization [Chen, TED] (b) Proposed layout (a) Thin layout

34. ACS Memory Array Setup

35. ACS Design Space Exploration Diameter-Write latency Diameter-Write energy Diameter-Read energy/Latency Chirality-Read energy/Latency Doping – write latency Doping – write energy Doping –read latency/energy

36. Conclusions • Post-moore era calls for disruptive innovations to sustain Moore’s law • 3D Integration is a promising technology, we introduce the work on PDN and thermal co-optimization to improve workload execution performance without violating temperature limit. • STT-MRAM is a competitive candidate for on-chip last level cache, we introduce the work on saving write energy by exploiting on-chip thermal gradient • Carbon-nanotube is suitable for both FET devices and interconnects, we explore the possibility and potential benefits of all carbon SRAM compared to the most advanced FinFET technology, and show the bright prospect of CNT integrated circuits.

37. There are still a lot of things to do (Monolithic / TSV-based) 3D Integration Ascend Another Storey to Have a Further Sight retrospect and prospect – Zhihuan WANG (Tang Dynasty)

38. Thanks for all my students in CADETlab! Thanks for our collaborators! Thanks for our sponsors!