Low Power Design for Portable Devices

1. Low Power Design for Portable Devices A investigation of techniques for the advancement of portable electronics By: Patrick Gonzalez Project Advisor: Dr. Baback Izadi Project Co-Advisor: Dr. Damu Radhakrishnan

2. Outline • Introduction • Proposed PDA • VLSI Level Low-Power • System Level Low-Power • DC Power Systems • Review Proposed PDA • Accomplishments • Current-Future Work • Conclusion

3. Introduction • Portable Devices are: • Everywhere • Here to stay • Advancing in capabilities rapidly • In serious need of more power

4. Why Low Power? • Power is expensive, non-renewable, and negatively impacts the environment • Extending life of battery powered systems • Increased desire for complex devices equals greater need for power efficiency • Reliability is cut in half for every 10oC rise in temperature

5. Project Background • Low power design group • Research several areas of low-power design • Proposed theoretical low-power PDA • Tested validity of new design • Researched three main areas • Investigated new design possibilities for each

6. Dynamic Power Consumption PDynamic = VDDVSwingCloadaf + VCCI sc + VDDIl 1 2 3 • Switching Power • Short-Circuit Dissipation • Leakage

7. Switching Power • Gate capacitances of gate inputs connected to output • Interconnect capacitances • Diffusion capacitance of drains

8. Short-Circuit Dissipation • Current flows from Vdd to ground • 0 if Vdd<VtN+ |Vt|

9. Proposed PDA • Dual-processor • Specially designed ultra-low-power • High-performance • Dual battery design • SDRAM & Flash memories • Solar cell

10. x + VLSI Level Techniques • Adders • Recent interest • Common unit • Multipliers • Power hungry • Created using adders • Common unit

11. Cout = HA + HCin CMOS Adders Equations H = A Å B • Conventional Design • 28 transistors • Static logic • Slow • Power hungry Sum = H Å Cin • Recent Design • 14 transistors • Pass logic • Fast • Low-power

12. CMOS Adders Cont. • XOR / XNOR • 6 Transistors • Full voltage swing • Voltage scalable • Fast

13. CMOS Adders Cont. • Personal Investigation • 2 XOR / XNOR modules (12T) • Simple 2-1 MUX for Co output (4T) • Requires only 2 standard cells

14. CMOS Adders Cont. • New Full Adder Circuit Features • 16 Transistor design • Full voltage swing at all nodes • Simple layout with fewer standard cells required (2) • Extra complementary sum output (discussed later) • Completely functional • Size, power, and delay currently being investigated

15. CMOS Multipliers • Conventional Design • Booth encoded for fewer partial products • Wallace tree structure for reducing partial products • Fast CSA or CLA for final addition

16. CMOS Multipliers Cont. • Partial Product Reductions • 4-2 Compressor • Cout & C have same weight • Often using 2 FAs • 40T, 32T, 30T, 28T

17. CMOS Multipliers Cont. • Personal Investigation • Consider a 3-2 compressor • 1st half of sum same as in standard full adder • 2nd half of sum equal to complement of standard FA sum • Cout is same, for each half, as that of standard FA • Carry is either 0 or ‘S’ depending on the value of ‘W’ • good candidate for new FA design

18. CMOS Multipliers Cont. • Personal Investigation Cont. • Expand to 4-2 compressor • Same general concept • XOR/XNOR of 2 MSbs control ‘S’ • Cout is repeated for every quarter block • Carry is either 1, 0, or S depending on XOR/XNOR value of the 2 MSbs • Can be simplified with reference to proposed FA

19. CMOS Multipliers Cont. • Personal Investigation Cont. • Expand to 4-2 compressor • Same general concept • XOR/XNOR of 2 MSbs control ‘S’ • Cout is repeated for every quarter block • Carry is either 1, 0, or S depending on XOR/XNOR value of the 2 MSbs • Can be simplified with reference to proposed FA

20. Cin W Z X Y FA + S XOR/XNOR I I Cout S S New 4-2 Compressor Cin Mux Mux Carry Carry Sum Cout Sum CMOS Multipliers Cont. Circuit Design • Proposed FA • XOR/XNOR • 2 MUX • Total 30 Transistors

21. CMOS Multiplier Cont. • New 4-2 compressor details • Full voltage swing at all nodes • Strong noise margin • 30 Transistors (Equal to smallest design w/ full swing) • Usable for voltage range from 2|VT| and up • Requires only 2 standard cells to complete the layout

22. System Level Power Management • Scheduling • Static Scheduling • Dynamic Scheduling • Multiprocessor Investigation

23. Voltage Scaling • Static Scheduling • Compile-Time • Task Ordering • Dynamic Scheduling • Run-Time • Deadline Critical

24. Multiprocessor Investigation • Olsen & Morrow • 2 Processors • Control logic • Problems: • Deign requires multiple operating systems • Processors cannot share code or data

25. Multiprocessor Personal Research DL(vi, pj­)=SL(vi)-max{ti,jA, tjM}-min{ti,jA, tjM}+D (vi,pj)-E(vi,pj) Heterogeneous Multiprocessor Scheduling Decision Heuristic for Low-Power • vi ---------------- task i • pj ---------------- processor j • DL(vi, mj­) ----- the dynamic level of a task-machine pair (The lower DL is, the higher the • scheduling priority) • SL(vi) ----------- the static level of task i. (Larger value for long execution time tasks) • ti,jA -------------- data ready time • tjM --------------- processor ready time • max{ti,jA, tjM} - a task-processor pair with an earlier starting time will have higher • scheduling priority • min{ti,jA, tjM} - a task-processor pair with an earlier deadline time will have higher • scheduling priority • (vi, pj) ----------- if processor j executes task vi faster than the other processors, its value will be positive, which increases the scheduling priority • E(vi, pj) --------- a measure of how much power will be used if task i is performed on • processor j

26. DC Power Systems • Battery Operation • Anode oxidizes • (loses electrons) • Cathode reduces • (gains electrons) • Electrolyte • passes ions • allows equilibrium *

27. DC Power Systems Cont. • Continuous Battery Discharge Rate

28. DC Power Systems Cont. • Intermittent Battery Discharge Rate • Non-equal transfer between electrons and ions • Charge recovery • Level of recovery dependent on active and rest times

29. DC Power Systems Cont. • Research • Multi-cell Intermittent Discharge Techniques • Others investigations for pulse discharge involve immediate transitional battery switching • Proposed investigation into ramped voltage transitions for intermittent discharge

30. DC Power Systems Cont. • Zero-delay ramped voltage switching • Extended rest ramped voltage switching

31. Proposed PDA Design • Dual-Processors • Ultra-Low-Power Processor • Same instruction set (close) • Shared pipelines (code & data) • Dynamic Scheduling • Static Scheduling (Compile-Time) • Dynamic Scheduling (Run-Time) • Multi-Battery Supply • Efficient voltage switching

32. Accomplishments • Attained solid background in low-power design techniques as required for future investigations • Created full reference document for members of the low-power group • Created theoretical PDA design for group research involving several areas of engineering • Validated several PDA design areas worthy of future research • Sending out a conference paper on the new 4-2 compressor

33. Current & Future Work • Currently involved in VLSI, Scheduling, & Multiprocessor techniques • Research other areas (memory, solar charging,…) • Develop mature design • Expand research group (Faculty, Grad, Undergrad)

34. Conclusion • Low-Power Design • Absolute necessity • Environmental – Toxic materials, CA energy crisis • Economic – Demand for portable electronics • Safety – Police, Fire, EMT, Forestry, … • Manufacturability – Faster processors require lower power • Possible at all levels • Complete redesign of current device architectures

35. Acknowledgments • Dr. Baback Izadi & Dr. Radhakrishnan • Judy Depuy • John Aurrichio • My fellow classmates and all others present

36. Any Questions?