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Top-level Schematics and Integration Status

Spice-level simulation strategy and Project tracking. Top-level Schematics and Integration Status. Top-level SPICE Sims Current top-level schematics Objectives: SPICE vs HDL Simulation strategy Preliminary results. Outline. Design Data Management EDA data sharing tools

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Top-level Schematics and Integration Status

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  1. Spice-level simulation strategy and Project tracking Top-level SchematicsandIntegration Status CERN FEI4 Review - Dario Gnani - LBNL

  2. CERN FEI4 Review - Dario Gnani - LBNL Top-level SPICE Sims Current top-level schematics Objectives: SPICE vs HDL Simulation strategy Preliminary results Outline • Design Data Management • EDA data sharing tools • Project tracking flow • Current repository status • Current top-level schematics

  3. CERN FEI4 Review - Dario Gnani - LBNL All digital and analog design files are stored in a locally-cached repository integrated with Cadence EDA tools: Cliosoft SOS All spec/interface documents are posted on CERN SharePoint EDA data sharing tools (1) • Collaboration across 5 different countries, 2 continents/timezones, and several designers • Complex file types (cadence libraries)

  4. CERN FEI4 Review - Dario Gnani - LBNL EDA data sharing tools (2) Out of sync checked out locally

  5. CERN FEI4 Review - Dario Gnani - LBNL Design Compliance DRC (cell-level, incl. local density) LVS/ERC (ports, swaps, props, isol wells) Line mode checks (IBM+Xstream) T3 policies Supply policies Naming conventions,... Project Tracking • Database Integrity • Complete check-in • Correct tech (e.g. vias) • Complete hierarchy • Cross view checks (e.g. check&save, portOrder) • Std names for ref libs • Lib props (e.g. metal stack) • [pcell CDF check]

  6. CERN FEI4 Review - Dario Gnani - LBNL Repository status chart

  7. CERN FEI4 Review - Dario Gnani - LBNL Higher Level Integration (1)

  8. CERN FEI4 Review - Dario Gnani - LBNL Higher-level Integration(2)

  9. CERN FEI4 Review - Dario Gnani - LBNL Top Level Schematic

  10. CERN FEI4 Review - Dario Gnani - LBNL HDL Extremely fast Easy to code complex tests Allows in depth functional verification Easy to detect timing errors On-chip variations (?) Cross-talk (?) IR / EM analysis (?) Timing sign-off Simulation Objectives: pros (1) • SPICE • Accurate description of analog blocks • Allows to verify chip power-up sequence • Validates HDL results in nominal conditions (or under corner/mismatch conditions) • Verifies timing arcs crossing analog blocks (e.g. SR) • ...

  11. CERN FEI4 Review - Dario Gnani - LBNL Results 30min/usec @ digCore level (67M FETs) Reset and clock only Pure SPICE Runtime will possibly double once complete Analog activity has to be limited Simulation Objectives (2) • Test • HSIM capacity • Testbench options • Simple spice (reset) • VCD • MixedMode (VCS/Modelsim) • Verification options • VCD • HSIM CircuitCheck

  12. CERN FEI4 Review - Dario Gnani - LBNL Preliminary results (1) Long delay: - intentional? - mismawired? - bug?

  13. CERN FEI4 Review - Dario Gnani - LBNL Preliminary results (2) Oscillations: - bad OP? - real?

  14. CERN FEI4 Review - Dario Gnani - LBNL Preliminary results (3) Clkreadfifo unaffected by reset: - makes its phase wrt main clk undetermined

  15. CERN FEI4 Review - Dario Gnani - LBNL SPICE simulations Simple simulation of 67M FETs completed in reasonable time All SPICE level verifications will be limited to very specific targets with very localized accuracy Summary • Design Status • Almost all blocks ready at the schematic/gate-level • Majority of layouts close to final • Interfaces are undergoing final tuning • Higher level schematics are being built and tested

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