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OGTI: Pre-Manufacture Review

OGTI: Pre-Manufacture Review. 1st September 2008 Draft. Optical Global Trigger Interface Why necessary In the original GCT project the GCT-GT interface was at the extreme limit of design specs. Switching to to a shorter cable was sufficient to break the system. Capable of both:

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OGTI: Pre-Manufacture Review

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  1. OGTI: Pre-Manufacture Review 1st September 2008 Draft OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  2. Optical Global Trigger Interface Why necessary In the original GCT project the GCT-GT interface was at the extreme limit of design specs. Switching to to a shorter cable was sufficient to break the system. Capable of both: Transmitting (Tx) Receiving (Rx) GCT-Tx and GT-Rx Electrons, Jets, EnergySums and JetCounts GT-Rx only for Muon MIP/Quiet bits What is the OGTI ? OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  3. Design One double CMC card POP4 /4 PMC Header PMC Header VCCO = 1.5V or 2.5V (3.3V ?) POP4 Xilinx XC5VLX110T FF1136 /4 PMC Header PMC Header 160 POP4 /4 PMC Header PMC Header 160 1.6 Gb/s (data) Split PMC header into 2 parts: PSB requires - 152 GTLP (1.5V) - 137 x LVTTL/LVDCI33 (3.3V) Concentrator requires - 144 LVDCI25 (2.5V) POP4 VCCO = 2.5 (3.3V ?) /4 PMC Header PMC Header Which CMC headers should be GTLP? OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  4. Top Side VREF-M POP4 decoupling +1.2V POP4 +3.3V I/O at +2.5V +1.0V Debug LEDs I/O at +1.2V XC5VLX110T-3FF1136C Debug Header GBT decoupling +2.5V A+1.0V +1.8V I/O at +2.5V A+1.2V JTAG header OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  5. Bottom Side x4 buffers MGT clock ac coupling Header decoupling Local Osc 2 Local Osc 1 Clk distribution to GBTs via two 4x4 X-point switchs FPGA decoupling. Some V5 packages, including our has built in decoupling. OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  6. StackUp L01 (TOP): L02: A+1.2V, +1.0V, +1.8V, VCCO-M (+1.2V) L03: High Speed Serial Transmit L04: GND L05: High Speed Serial Receive L06: A+1.0V, VREF-M, +5V L07: +2.5V L08: Spare L09: +3.3V L10: Clock Distribution L11: GND L12 (BOT): FPGA Core, Prom & I/O Ref Voltage: +1.0V, +1.8V and VREF-M High speed serial: A+1.2V and A+1.0V I/O Power & Input Power: VCCO-M (+1.2V) and +5V OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  7. Specs Thickness 1.6mm max Otherwise will not fit GT crate Through via (Min 0.25mm) layers 1 to 12 depth = 1.6mm Blind Top via (Min 0.2mm) layers 1 to 6 depth = 0.8mm Blind Bottom via (Min 0.2mm) layers 7 to 12 depth = 0.8mm Board Specifications OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  8. POP4 power dissipation HFBR-7934Z = 1.0W (typ), 1.46W (max) ZL60304 < 1 W Total Opto Power Dissipation = ~4W Xilinx power dissipation 16 GBTs @ 100mW ~1.6W 160 GTLP Out + 80 LVDCI33 In + 80 LVDCI33BiDir ~1.8W Internal logic ~1-2W Total FPGA power ~5W Power dissipation OK in airflow. Power Consumption OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  9. Input power Everything powered from +5V. Output Power Datel LSM-10A switchers: FPGA I/O: +1.2V & +2.5V FPGA Core: +1.0V POP4: +3.3V PROM: +1.8V (bit overkill) back order cancelled change? MAX8556ETE linear GBTs: A+1.0V and A+1.2V I/O Ref: VREF-M Power Supply OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  10. 4 4 4 4 SN65LVDS125 Cross-Point Switch In: 0 Out: 0 In: 1 Out: 1 In: 2 Out: 2 In: 3 Out: 3 Clock Distribution OSC1 OSC2 CLK40 CLK80 SN65LVDS125 Cross-Point Switch SN65LVDS104 In: 0 Out: 0 For GBTs (progammable) SN65LVDS104 In: 1 Out: 1 4 In: 2 Out: 2 In: 3 Out: 3 SN65LVDS104 SN65LVDS104 For GBTs (progammable) 4 For fpga fabric (fixed) 4 For micro-coax (fixed) 4 OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  11. Schedule & Status • Still to do: • Still need to resolve power plane issues. • Some minor mods for the GT. • Possible replace +1.8V switcher with small linear. • PCB manufacture & assembly in September/October. • Design will be checked by Pads expert prior to submission. • Manufacture & Assemble 2 PCBs OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  12. Appendix OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  13. Global Trigger interface GT receives 7 cables (2 unidirectional SerDes channels per cable) Each channel driven by NatSemi DS92LV16 Takes 16 bit parallel data at 80MHz. Adds 2 bits. Transmits at 1.44 Gb/s Require 2 bits for powerdown/sync 252 signals (7 x 2 x 18) Require 1 cable for loopback testing Generates 16 bits parallel data Require 4 bits for lock, refclk, powerdown and recovered clk 40 signals (1 x 2 x 20) NatSemi chips do not have JTAG Could use local loopback to test data lines only. Require 2 bits for outenable and local loopback on all chips 44 signals ((14 x 2) + 16 Mounted on dual PMC All 380 I/O connected, Require at least 292 signals, perhaps 336 Slink Signals connect to VME J2 and hence to ECAL transition card GT interface OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  14. Height: Concentrator Vertical heights to scale Misc 1.8mm OptoGTI, 1.6mm POP4 Opto 13mm No heatsink on AvagoTech POP4 Small heat sink on Zarlink POP4 Clearance for components on concentrator is tight. Components used for spare LVDS RJ45 in/out jack & USB. Components can be removed or insulated with kapton tape if necessary Connector 15mm Misc 1.8 mm Concentrator, 1.6mm OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

  15. Height: PSB Vertical heights to scale Misc 1.8mm OptoGTI, 1.6mm POP4 Opto 13mm No heatsink on AvagoTech POP4 Small heat sink on Zarlink POP4 15.4mm Connector 12mm PSB, 1.6mm 18.8mm Misc 1.8mm ? Total height violates VME spec, but wil fit assuming assumptions used for caps, etc on back side of boards OK. OGTI: Pre-Manufacture Review (g.iles@imperial.ac.uk)

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