1 / 12

An MWPC Readout Chip for High Rate Environment

An MWPC Readout Chip for High Rate Environment. Introduction ASIC Structure & Fabrication ASIC Evaluation A VME based MWPC Readout System Summary. Chikara Fukunaga at Tokyo Metropolitan Univ. on behalf of the ATLAS TGC electronics group. Introduction.

zanna
Download Presentation

An MWPC Readout Chip for High Rate Environment

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. An MWPC Readout Chip for High Rate Environment • Introduction • ASIC Structure & Fabrication • ASIC Evaluation • A VME based MWPC Readout System • Summary Chikara Fukunaga at Tokyo Metropolitan Univ. on behalf of the ATLAS TGC electronics group IEEE NSS 2000 at Lyon,France

  2. Introduction • Construction of General-purpose MWPC readout system with customized ASIC • Primary goal is for a test system of ATLAS Thin Gap Chambers (TGC) • High rate • Large scale and huge amount of read out channels • Binary readout IEEE NSS 2000 at Lyon,France

  3. ASIC system 1 – Readout Block • Binary input from ASD • LVDS to TTL • Polarity control • Synchronization • 100 stage shift registers pipeline for trigger latency • Most of blocks are built from standard cells One channel readout IEEE NSS 2000 at Lyon,France

  4. Hit channel No hit channel ASIC system 2 – Timing Charts(working principle) IEEE NSS 2000 at Lyon,France

  5. ASIC system 3 – an LVDS cell • A Standard diff. to single ended signal converter • Differential Amp. • Two inverters • Drivable to 200 MHz frequency IEEE NSS 2000 at Lyon,France 33mm

  6. ASIC mask pattern • ROHM CMOS 0.6mm • Die size 4.5 x 4.5 mm2 • 8000 Gates • Full-custom • Package QFP160 • LVDS block isolated from Main Digital block IEEE NSS 2000 at Lyon,France

  7. ASIC evaluation • Current dissipation vs. driving frequency (VDD=5V) • 25 MHz LVDS pulse input • Up to 200 MHz the ASIC works normally. • Driving voltage:LVDS input • For both 5 and 3.3V, Input range of LVDS covers standard one of 0 and 2.4 V. IEEE NSS 2000 at Lyon,France

  8. MWPC readout system with ASIC • VME based system • Special J2 backplane • Components • VME crate + special J2 • ASD (Amp.+Shaper+Discl.) • A Control Signal Distributor (CSD) • Signal Latch (SL) modules • VME controller + PC IEEE NSS 2000 at Lyon,France

  9. ASD board(Amp.,Shaper,Discriminator) • For ATLAS TGC to readout wires/strips in binary mode • High background • High radiation • 4 ASD chips (16 ch.) (4 ch./chip) • Stable operation for up to 100 KHz IEEE NSS 2000 at Lyon,France

  10. CSD Distribution of Control signals of DAQ (CLK,TRIGGER,Gate width,Reset) for SLs Event ID numbers for SLs Threshold volt., test pulse for ASDs via SL SL Operation of 4 ASICs (64 channels) Latch signals with TRIGGER Input ASD binary data (Front Panel for 4 ASD boards) CLK,TRIGGER etc.(J2) Output 64 channels hit pattern (FIFO and J1) +3.3V for ASD CSD (Control Signal Distributor) and SL (Signal Latch) IEEE NSS 2000 at Lyon,France

  11. Evaluation of an SL (ASIC & COTS) • Two versions of SL • COTS (64 channels) • ASIC (64 -> 128 channels) IEEE NSS 2000 at Lyon,France

  12. Summary • ASIC for MWPC readout system has been made. • Shift register pipeline for high rate environment • VDD of ASIC can be down to 3.3 V • Frequency up to 200 MHz • VME based MWPC has been constructed with ASIC • Power,Cost,Size are downed to 1/2 • This system will be used for the ATLAS TGC test bench. IEEE NSS 2000 at Lyon,France

More Related