CAD Contest Progress – Lab231-Cix

1. CAD Contest Progress –Lab231-Cix Member: Chih-Chung, Wan-Chen, Chia-Yao, Sharon Speaker: Wan-Chen Date: 2013/08/14

2. Outline • Proposed flow • Progress • Schedule

3. Proposed Flow

4. Progress - Mapping • Ex: • and/or/nand/nor : find AND node(use structure directly) • adder/multiplier: find FA and its sub-functions (cut-based) • hybrid: see it as either adder or multiplier • index: find multiplexer

5. Progress - Mapping • Finding continuous ANDs in the design → OK. • Finding continuous ORs in the design → OK.

6. Progress - Mapping module lib1(in1, in2, out); input [1:0] in1; input [3:0] in2; output out; assign out = in2[in1]; endmodule In1[1] In1[0] In2[3] In2[2] out In2[1] In2[0]

7. Progress - Mapping • Design: • Finding continuous ORs. • Finding 2n ANDs and every AND has (n+1) inputs. • “n” is # of selectors.

8. Progress - Mapping • Design:

9. Progress - Mapping • Design to library: S0 S1 A B out C const. 0

10. Progress and Schedule

11. Progress and Schedule • Cut & Mapping: Wan-Chen, Sharon • Parser bug & Output: Chia-Yao