Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

1. Binding, Allocation and Floorplanning in Low Power High-Level Synthesis A. Stammermann, D. Helms, M. Schulte OFFIS Research Institute A. Schulz, W. Nebel Univ. Of Oldenburg

2. Outline • Motivation • Background • Optimization Algorithm • Evaluation • Results • Conclusion ICCAD 2003

3. Motivation Within actual CMOS-technologies (0.1m) 80-95% of the power consumption emerges from charging and discharging capacitances. VDD Input Output Switching activity  Capacitance of • gates at the output • connecting wires C GND Pdyn =  C VDD2 f Optimization target ICCAD 2003

4. Capacitance Distribution (ITRS Roadmap 2001) Increasing share of interconnect capacitance Interconnect has to be considered during high-level synthesis. ICCAD 2003

5. Summary • Capacitance contributes linear to power dissipation • Wire capacitance is increasing • Wire capacitance is dominated by its length  Thus it is important that accurate physical information is used during high-level synthesis ICCAD 2003

6. rough Floorplanning detailed Floorplanning ASIC-Cells Chip Design RT-netlist Generation adder, multiplier Gate-netlist Generation Increasing level of details Floorplanning ASIC-Cells Interconnect ICCAD 2003

7. +1 +2 +3 +4 +5 cstep 1 +1 +1 cstep 2 +2 +2 cstep 3 +3 +4 +3 +4 +5 cstep 4 +5 RT-Netlist Generation Scheduling When are operations executed Allocation How many resources Binding Which operation is executed on which resource ICCAD 2003

8. +1 +1 +2 +2 +3 +4 +3 +4 +5 +5 RT-Netlist Generation Reg1 Reg2 Reg3 Reg1 Reg2 Reg3 ADD1,2 ADD3 ADD4,5 ADD1 ADD2,3 ADD4,5 ICCAD 2003

9. 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 +1 +2 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 ADD Impact on Power Dissipation • Binding/Allocation • Interleaving changes the characteristic of input streams:The switching activity  at the input of resources (and according wires) can increase or decrease. • Influences netlist topology:The wire length resp. capacitance can increase or decrease. ICCAD 2003

10. Power Estimation • Switching activity Simulation of behaviour description • Power consumption of resources (e.g. adder) Power models • Wire capacitance Capacitance model Floorplan ICCAD 2003

11. x x y y 3 * 1 + + * 5 3 5 2 4 1 2 4 Floorplanning • Slicing Floorplans • Standard • Supports softmacros (leafs are flexible in their aspect-ratio) • Efficient representation as binary tree vertical horizontal ICCAD 2003

12. Optimization Algorithm Power optimization algorithm for RT-level netlist with regard to interconnect power • Performs simultaneoulsy • Slicing-tree structured based floorplanning • Functional unit binding and allocation • Changes in the netlist topology are mended immediately in the actual floorplan • In contrast to previous approaches a generation from scratch is not necessary • Non-deterministic, iterative optimization technique • Simulated Annealing • Cost function: PFE + PInter + Area ICCAD 2003

13. 2 1 3 4 * + 3 * + + + 2 3 2 4 1 4 1 1 2 4 3 Floorplan-Annealing Simulated Annealing based floorplanner Floorplan moves • F1: Exchange two leafs • F2: Exchange leaf and node • F3: Change direction • F4: Exchange two nodes • F5: Displace a leaf / node F2: Exchange leaf and node ICCAD 2003

14. Initial Floorplan new costs < old costs Stopping criteria met? Optimized floorplan Floorplan-Annealing Floorplan move Fi random number < e-Cost/T Undo move Fi N N Y Y Y N Y ICCAD 2003

15. Architecture-Annealing Architecture moves (mutate binding/allocation) • A1: Share • Merge two resources res1 and res2 to one single resource • res1 und res2 must be instances of the same type (e.g. ripple adder) • A2: Split • Inverse of Share • Split a single resource into two resources • A3: Swap • Swap the inputs of commutative operations A1-A3 in combination are able to create every possible binding solution ICCAD 2003

16. Architecture-Annealing Changes in the architecture are mended immediately in the actual floorplan. • Moves A1-A3 may cause resources to vanish or appear. • Moves A1-A3 changes the netlist topology. The floorplan is not optimal anymore after a move A1-A3. Solution: • Each move A1-A3 is followed by a floorplan update (annealing). • Supporting softmacros. • Optimal inserting of new resources into floorplan. ICCAD 2003

17. new costs < old costs Stopping criteria met? Optimized architecture/floorplan solution Algorithm Initial architecture/floorplan solution Each architecture move is followed by a floorplan-annealing Architecture move Aj floorplan- annealing random number < e-Cost/T • Undo move Aj • Undo floorplan update N N Y Y N Y ICCAD 2003

18. new 1 1 3 3 2 new 4 1 2 4 hardmacros 8.2 LE 3 1 2 1 4 3 3 best position 2 new 4 2 new 4 4.6 LU softmacros Inserting new resources ICCAD 2003

19. Evaluation 3 experiments are performed: • Full parallelEach operation is mapped on one single resource (no resource sharing). • ConsecutiveBinding optimization and floorplan optimization are executed consecutively. This interconnect unaware optimization is similarly to the traditionally procedure in high-level synthesis. • SimultaneousBinding and floorplanning is optimized simultaneously. ICCAD 2003

20. Results ICCAD 2003

21. Conclusion • Compared to consecutively (traditionally) procedure the proposed technique • reduces interconnect power almost by half • increases the functional unit power insignificantly • The CPU times vary from 6 seconds (diffeq) to 138 seconds (turbo_decoder).[1,0 GHz Athlon™ based PC with 256 MB memory] ICCAD 2003

22. Thank You! ICCAD 2003

23. Capacitance model Capacitance extracted from layout vs. capacitance from our model (0,35 m) ICCAD 2003

24. ITRS Roadmap 2001International Technology Roadmap for Semiconductors ICCAD 2003

25. Cross Section on Die ICCAD 2003