Width Minimization In the Single-Electron Transistor Array Synthesis

Width Minimization In the Single-Electron Transistor Array Synthesis Speaker: Chian Wei Liu Advisor: Dr. Chun-Yao Wang 2014/03/10

Outline • Introduction • Motivation • Problem formulation • Width minimization approach • Product term extraction • Variable reordering • Hybrid architecture determination • Product term reordering • Overall flow • Experimental result • Future work

Introduction • Single-electron transistor array • A graph composed of hexagons • All sloping edges are configurable:short, open, active (high or low) • Active edges at the same row are controlled by a single variable active high active high a active low active low a short short current detector open open current detector b b (high,low) (high,low) (high,low) (high,low) 1 1

Introduction • Mapping constraints • Granularity constraint • Two edges are configured simultaneously • The combination of left and right edges must be one of (high, low), (low, high), (short, short),and (open, open) in the SET array. • Fabric constraint • (high, low) and (low, high) cannot simultaneously appear in a row 0110 010- 11- - Constraint free Granularity constraint Granularity & Fabric constraint

Introduction • Branch-then-Share product terms • The pair of product terms will branch at one row and merge in other row, after the merging point the remaining variables should be the same value • Case: (01,10), (1-,01), (0-,10) • Case: (0011,1100) ,(00-1,11-0) , (00--,11-0) ,… 000111 011001 001001 010001

Motivation • The previous work focuses on reducing the number of hexagons in SET arrays while the area is more related to the width. 1 1 -3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3

Problem Formulation • Given: • A Boolean circuit and its linear threshold gate(LTG) network. • Objective: • Configuring the circuit into SET arrays result in the smaller width. Boolean circuit Our approach LTG network 1 -3 -2 -1 0 1 2 3

Key idea • Reducing numbers of product terms • Architecture relaxation • We allow both (high, low) and (low, high) to appear in an SET array

Key idea • Branch-then-Share creation • Relaxing architecture to create more type of Branch-then-Share • If they are Bran-then-Share, there are only 2/4 different variables between them • Reordering the variables to create the Branch-then-Share product term abgcdef abcdefg --110-111 --110-110 --1101101 --110-000 --1100001 --1010001 --00-0000 --11- 1110 --11- 1100 --1111010 --11- 0000 --1100010 --1000011 --000000- Twin type : (high, low) : (high, low) (low, high)(low, high) Invert type : (high, low) : (low, high) (low, high)(high, low)

Product term extraction from threshold networks • A threshold network is a network composed of linear threshold gate(LTG) • Computing product terms from LTG networks • Swapping the symmetric inputs The equation and symbol of a LTG

Computing product terms from LTG networks • Assuming the weights are integers • The weights of an LTG are positive • Computing its disjoint product terms from the primary output (PO) towards the primary inputs (PIs)

Computing product terms from LTG networks

Swapping the symmetric inputs • Swapping these symmetric inputs so that each don’t care “–” corresponds to a larger faningate • For the LTG in the PO, only recording the locations of “–” from its onset • For other LTGs, recording the locations of a don’t its onset and offset

Swapping the symmetric inputs F a a a d n3 n3 e e n2 n1 n2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b b b 1 3 1 1 2 2 3 1 1 3 2 c c c e d f f d n1 n1 n2 n3 1 1 1 f F f

Product term extraction • Product term computation from linear threshold networks • Product term computation from Boolean networks • Choosing the network with fewer product terms Boolean circuit BDD extraction selection A set of product terms LTG circuit LTG extraction

Variable reordering • Moving all share variables to the front • Reordering the remaining variables according to the quantity of the bit value

Variable reordering • Labeling the 2 different bits of all the Branch-then-Shares • Reordering variables according to the quantity of Branch-then-Share it can provide a: b: c:dd d: e: f: g: h h h: i: f fff b ->e ->a ->i ->f ->c ->d ->g ->h

Branch-then-Share collection • The conflicts among Branch-then-Shares • Type conflict • The invert type and twin type occur in the same variable • Under the fabric constraint, one variable can only has one configuration so the invert type and twin type is impossible to occur in the same variable • Group conflict • There are more than one share groups in one product term • The pitfall invalid path may be conducted Type conflict Group conflict Conducted paths P1: 11011 P2: 10-11 P4: 10-00 Invalid: 11000

Branch-then-Share collection • Collecting all type of the Branch-then-Shares. • Checking conflicts. • Selecting maximum share group and eliminating other conflicts

Hybrid architecture determination • The first row is always configured as (high,low) • When there is a Branch-then-share, determine the row structure to meet the Branch-and-share requirement • Other row structures are determined as the previous row structure if over half of variables changes their value.Otherwise, inverse the row structure

Product term reordering • Grouping product terms • Scanning all the product terms from the first variable to the last one until at least one of product terms have different bit values on the variable • Calculating the lowest location of Branch variable among the Branch-then-Shares • Product term ordering determination • Determine the product term order by share collection and group relation • Priority: share collection > group relation

Product term reordering P1~P7 --1 --0 P1~P6 --11 --10 P7 --110 --111 P1,P5,P6 P1,P5 P1,P3,P5,P6 P2,P4 P1->P2->P5->P4->P3->P6->P7 --1100 --1101 P3 P6

Overall flow A LTG circuit A Boolean circuit Architecture determination Configure the first row architecture as (high, low). Configure the following row architectures according to the share type and quantity of the switchingamong the product terms. Product terms computation BDD-based method LTG-based method Fewer product terms Product terms reordering Variables reordering Grouping the product terms. Calculate the lowest location of Branch variables among the Branch-then-Shares. Determine the ordering according to the group relationship and Branch-then-Share relationship. • Move all-shared variables to the front. • Reorder remaining variables according to the quantity of bit values in the variable among all the product terms. • Label the 2 different bits of all the Branch-then-Shares. • Reordering variables according to the quantity of Branch-then-Share it can provide. Mapping process Branch-then-Share collection Collect all the Branch-then-Shares. Check conflicts. Select maximum share group and eliminate other conflicts. SET arrays

Experimental result

Future work • Considering 4 bits Branch-then-Share • Starting to organize the paper

Width Minimization In the Single-Electron Transistor Array Synthesis