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FIELDS TDS FPGA Peer Review

FIELDS TDS FPGA Peer Review. Keith Goetz University of Minnesota Goetz@umn.edu. TDS. Time Domain Sampler TDS is a combination of analog electronics, digital electronics, VHDL firmware and flight software Added System-6 pieces fit in well Low impact TDS FPGA is central

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FIELDS TDS FPGA Peer Review

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  1. FIELDS TDS FPGA Peer Review Keith Goetz University of Minnesota Goetz@umn.edu

  2. TDS • Time Domain Sampler • TDS is a combination of analog electronics, digital electronics, VHDL firmware and flight software • Added System-6 pieces fit in well • Low impact • TDS FPGA is central • RTAX4000 is the FPGA of choice • RTAX4000SL-1 CCGA-1272 • Maybe more than we need in gates but has lots of pins • CQ352 does not have enough user pins • FIELDS FPGA daughter board makes this a common part/design solution

  3. TDS FPGA Block

  4. TDS FPGA Block

  5. TDS Data Acquisition/Control • Gather time series data • Access ADCs • Front end processing • Acquire SWEAP counts and sync • Down sampling e-time series • Send buffered data stream to TDS memory controller • Never skipping a beat • Generate sampling clock • Select muxes

  6. TDS statistics Peaks and maxes Triggering Langmuir wave statistics Dust analysis High heritage

  7. TDS Memory Control • Accept data steam • Accept triggers • Control circular buffers • Large dedicated 32-bit memory path • Large dedicated event memory (16MB) • Interleave memory access from CPU

  8. TDS FFT Controller • Optional • Allows frequency analysis • Redundancy • Enhances dynamic range of new all-digital TNR • Large signal spectra • Could be done in hardware or software

  9. HK ADC Controller • New • Allow FSW access to external ADC/MUX • Analog HK • Analog Science

  10. S/C TM/TC Interface • New • UARTS to/from S/C • A/B • S/C Time, Status and Sharing • S/C commands • S/C telemetry • HK • MAGi • Provides one real-time clock • Common VHDL and FSW with DCB

  11. Clocks • Receive internal clock (from on-board oscillator) • Receive external clock (from DCB) • Fail-over and back • Slave to DCB when possible • Generate clocks for internal/external use • MAGi CDI (4.8MHZ) and heater (300kHz) • SWEAP CDI (4.8MHz) and high-rate clock (19.2MHz) • AEB2 conversion clock (300kHz) • LNPS2 conversion clock (600kHz) • ADC clocking • Maintain real-time clock from S/C • Maintain real-time clock from DCB

  12. Watchdog • Handles resets • Internal watchdog timer • Touched by FSW • If not touched delivers a reboot • Generally, the watchdog time is long • 220s in the past

  13. DCB CDI • Standard CDI slave interface • 4.8MHz • Also includes high rate clock (38.4MHz) • DCB sends TDS time and commands • TDS sends DCB fully formed TDS CCSDS data packets • ~10kbps • Common VHDL and FSW with DCB

  14. MAG CDI New Standard CDI master interface 4.8MHz Also includes power supply chopping frequency (300kHz) TDS sends MAG time and commands MAG sends TDS data chunks – one per cycle Common VHDL and FSW with DCB

  15. SWEAP CDI • New • Standard CDI master interface • LVDS • 4.8MHz • Also includes high rate clock (19.2MHz) • TDS sends SWEAP time and commands • CBS • MAG vector • Once per cycle • SWEAP sends contributions to CBS

  16. AEB Interface • New • Parallel and serial interface lines • Controls Antenna Electronics Board parameters • Current and voltage biasing • Retrieves AEB HK • Controlling AEB MUX • Also includes power supply chopping frequency (300kHz) • Common VHDL and FSW with DCB

  17. LNPS Interface • New • Parallel interface lines • Controls MAG power • Retrieves LNPS HK • Controlling LNPS MUX • Also includes power supply chopping frequency (600kHz) • Common VHDL and FSW with DCB

  18. Test UARTS • Console • OOB commanding • Log • OOB event stream • GSE • OOB binary/packet data stream • Debug • Line drivers on GSE (mezz board)

  19. Test points • Board serial number • Blinking light • Software controlled • Test input ports • Test output ports • I/O to EM connector to allow timing/triggering tests

  20. Processor • LEON 3 IP • Free – open source • SPARC V8 • LEON 3 FT planned for flight • STEREO used an earlier version – SPARC V7 • IP • Gaisler GRLIB • LEON • AHB/APB infrastructure • GDB • GRMON • UARTs

  21. Processor Support • Interrupts • DMA Handler • Processor RAM • Internal and external • Processor ROM/PROM • Internal and external • Internal boot PROM? • Processor EEPROM

  22. Mezzanine Board • GSE only • RS-232 drivers • Reset button • Blinking light • Logic Analyzer interfaces • PROM/EPROM/EEPROM sockets • PROM emulator interface

  23. TDS BB2

  24. FPGA statistics

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