MAVEN Digital/FPGA Peer Review FPGA Design/Development May 12, 2010

1. MAVEN Digital/FPGA Peer Review FPGA Design/Development May 12, 2010 D. Gordon

2. FPGA Design Framework Synchronous Top Level Clock HCLK 16.8MHz for DCB, 8.4MHz for SEP, 1.0MHz for SWEA/SWIA 24MHz for STATIC Derived Clocks from DCB forwarded to instruments and LVPS Small State Machines Failure-Tolerant Operation by top level design Unit Testing is Contained Gray Coded Undefined States return to IDLE Resets HW_Reset_In is Conditioned as per Guidelines FPGA Global Reset = Conditioned Reset ORed with Watchdog Reset and S/C Reset for most DCB FPGA Modules ORed with Commandable Reset for most Instrument FPGA Modules

3. FPGA Design Framework (continued) SWEA and SWIA Anode Counters Faster than the System Clock Anode Counts arrive at a maximum rate of 10MHz Each anode counter is treated as a separate clock domain The Anode Counter domains are frozen for a few microseconds at the end of each accumulation interval while their totals are transferred to the SCLK domain and counters are zeroed.

4. FPGA Parts and Prototyping Two Type of FPGAs RTSX72SU-CQ208 for SWEA, SWIA and SEP Footprint compatible Protoboard Part: A54SX72A-PQ208 Flexibility exists to verify either part on the proto and/or flight board Use A54SX part with socket until design is fully checked out RTAX2000-1CG624 for STATIC and DCB Use A3PE3000-FG324 as Protoboard Part during development Two types of Daughter cards (for CG624 and FG324) Use of Daughter Card allows for footprint compatibility between Flight and Protoboards Can verify either part on the proto and/or flight board The AX2000-1CG624 is footprint compatible with the RTAX2000-1CG624 option for an interim test-step before programming the flight part

5. FPGA Development Process • All Module and Top Level code is tested/exercised • Stress testing (much of which is not possible at top level) is performed at module level (e.g. full “stackup” of requests to Memory Controller/Arbiter). State machines are taken through all branches. • Each module is functionally verified (testbench, tcl script). When feasible, data is written out in text format to ease regression testing. • Simulation/testbench framework established during Proto/ETU Phase. • Top level functional simulations write out log files (MBUS Traces, Telemetry and FLASH Logs). The text files saved and facilitate regression testing. Functional simulation results are compared to timing simulation results

6. Configuration Management Each FPGA Revision is numbered Revision log maintained, lists reasons and details for all deltas from previous version Revision Number is embedded in the FPGA Directory frozen/saved for each FPGA revision Source code, synthesis, stimulation, simulation, P&R can be retrieved for any revision Description and Module level history included in header to each HDL File Flight FPGA uses HDL identical to the Proto FPGA HDL linked to a common directory Minor differences due to architectural differences (i.e. memory instantiation)