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CMS Annual Review 2003 PACT - the RPC Muon Trigger Bari-Helsinki-Lappeenranta-Warsaw

CMS Annual Review 2003 PACT - the RPC Muon Trigger Bari-Helsinki-Lappeenranta-Warsaw. Jan Królikowski Warsaw University. PACT tasks. PACT ESR. The Electronics System Review of the PACT Muon Trigger was held on July, 8th, 2003 in Warsaw.

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CMS Annual Review 2003 PACT - the RPC Muon Trigger Bari-Helsinki-Lappeenranta-Warsaw

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  1. CMS Annual Review 2003PACT - theRPC Muon TriggerBari-Helsinki-Lappeenranta-Warsaw Jan Królikowski Warsaw University

  2. PACT tasks Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  3. PACT ESR • The Electronics System Review of the PACT MuonTrigger was held on July, 8th, 2003 in Warsaw. • The extensive documentation prepared for this review can be found at http://hep.fuw.edu.pl/cms/esr/ • This documentation reflects the present status of the project. Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  4. Outline • PACT layout and general characteristics • Progress since 2002 / Open issues • 2.1 UXC55: Link system • 2.2 USC55: Counting room electronics • Cost, schedule and milestones Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  5. 1. PACT layout and general characteristics Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  6. Coverage of initial systemin 20076-4 stations up to ~ 1.24 ; 3 up to  ~1.6 Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  7. PACT electronics: layout and main components Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  8. PACT inventory Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  9. Progress since 2002 • UXC55 electronics: • progress in the Link System prototypes and design. Now entering preparation of production phase. • Firming up of the LB boxes installation plans. • USC55 electronics: • progress in PAC algorithms and FPGA implementation of 4/6 plane algorithms, • VHDL codes for many components (sorters, GhostBusters) developed and tested, • New SorterCrate architecture • Overall organization of the project • New division of tasks between Bari/ Lappeenranta/ Warsaw Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  10. 2.1 UXC55 electronics: progress in the Link System Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  11. UXC55 electronicsSummary of progress in the Link system • Link Board + Control Board + Optical Link: prototypes successfully tested in the LHC-like beam in May 2003 • Monitoring of the RPC performance and test pulses – successfully tested as well. • Powerful diagnostic tools installed on the LB • Setting up of the RPC FEB parameters via I2C still to be tested. • Radiation tests of FPGAs and FLASH memories • Reloading of FPGAs on the LB every 4-10 minutes is sufficient • Safety aspects of DCS:progress since ESR • Integration and installation issues: constant progress Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  12. LB functionalities Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  13. LB RE1/1 prototype 2003 Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  14. Tested functionalities of Link System • Synchronization of signals from chambers • Histogram of signals in synchronization window • Histogram of all signals from chambers • Histogram “bx history” • “Snapshots” • Test pulses • TTCrx signals distribution • LB FPGAs loading from CB • CCU and VME interfaces Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  15. Beam testsHistograms The muon beam profile During the tests two RPCs were connected to one LB The „bx history” histogram - train of 48 bx’s with muons Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  16. Beam testsSnapshots Bx RB1 Channel RB2 Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  17. Conclusions from the LB system tests in May 2003 The histograms and snapshots work well and have proved their usefulness in testing the performance of chambers. TTCrx signals distribution, test pulses and FPGA loading work well. Optical link will be tested as soon as the quartz for the PLL is available Problems with CCU block transfer and I2C control of FEBs Solved by now Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  18. Measured SEU ratecaclulated SEU rate for the LB FPGAs • For the 72 RE11 LB with 72 FPGAs: • 7 SEU/1 h/ 72 FPGAs • For the remaining 1578 LB not at RE11 (with 1578 FPGAs): • 12.6 SEU/ 1h/ 1578 FPGAs Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  19. Conclusions of 2002 and 2003 radiation tests in Jyvaskyla Xilinx Spartan-IIE chips have small enough SEU in configuration bits Dynamic SEU are much less probable then SEU in configuration bits Reloading of the FPGAs every 10 minutes should guarantee that at most a few SEUs will be accumulated in all LBs FPGAs, what should not affect the system performance FLASH memories are resistant enough to radiation and will be used on final Control Boards More details http://hep.fuw.edu.pl/cms/esr/docs/RadiationTests.pdf Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  20. LB boxes (LBx) inventory Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  21. RE1/1 LB boxes – a special case Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  22. 2.2 Progress in the USC55 electronics Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  23. Progress in USC55 electronics Conclusions Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  24. PAC processor – progress in the VHDL codes Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  25. FPGA PAC in the barrel Example: performance of 1 type of FPGA Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  26. FPGA PAC in the endcaps Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  27. 3. Cost, schedule and milestones Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  28. New division of responsibilities in the PACT group Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  29. COST • We are revising the PACT CORE cost estimate. • At present, the CORE costs are 3750 kCHF, while our starting estimate in 1997 was 3695 kCHF. • This cost estimate is for the full trigger system up to eta=2.1 but without RE5. Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  30. COST contd. • Financing: • Finland 1020 kCHF • Poland 2060 kCHF • Bari 100 kCHF • TOTAL 3180 kCHF • + Korea 400 kCHF ? Almost enough for up to eta=1.6 Conclusion: either design a cheaper system or stage and hope for extra funding. Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  31. COST contd. • Main cost uncertainties/ drivers: • PAC FPGAs – assumed 300 CHF/pc, total amount for PAC FPGA 345 kCHF, • present cost of Stratix ALTERAs are higher but we expect them to fall to 300 CHF by 2005 when we have to buy them. • Splitter system – assuming 1000 CHF/ TB we get total amount for splitters 108 kCHF. The cost drivers are opto receivers (max. 20 on a TB, as well as one on a Splitter Bd) / opto transmitters. Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  32. Staging and Cost Saving • Presently approved strategy for PACT electronics construction: • Order elements for LB system for existing RPCs (up to eta=1.6, w/o RE5) and RE11 (difficulties in latter installation of LBx there). • Order elements and assembly Splitter System only for existing RPCs. • Order elements and assembly TB w/o PAC FPGAs for the complete system. • Order PAC FPGAs for towers up to eta=1.6 • If not out of money order more FPGAs/ Links. Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  33. Schedule defined Nov. ‘02 Update Sept.03 Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  34. Important forthcoming system test In the synchronous beam in June 2004 Test hardware and software for: RPCs + LB+CB + Optical Link+ Splitters+ +TriggerBoard+Readout Board+SorterBoard+ +interface to the GMT Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  35. Milestones defined Nov. ‘02 Dec 03 IImportant Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  36. Manpower (in FTE) • Warsaw: electronics engineers 2.5 • WUT students 2 • PhD students 1.5 • Technicians 1.5 • Programmers 0.8 • Finland: ? • Bari: electronics engineers 1.5 Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  37. Conclusions • COST: • Almost within estimates from 1997 • Still substantial uncertainties ( 10 %, maybe even up to 20%?) but firming up • SCHEDULE: • Tight • Critical path: LB RE11 box mechanics, splitters, trigger board • MANPOWER: • Still a worry • Recently more help from Finland (LB production and Splitters) • Warsaw manpower sufficient for USC55 electronics - TB/ ROB/TC • Bari: sufficient for Sorter Crate Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  38. Additional material Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  39. Test Pulses Sharpness of the Synchronization Window Test pulse directly connected to input channel with short (~5cm) cable Test pulse Synchronization window window open window close The sharpness of the synchronization window edge is ~0.3 ns (one channel) Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  40. Beam testsWindow Size and Position Scans Ratio of chamber noise signals in synchronization window to all measured. The beam bunch time shape scanned with 1ns window Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  41. Test PulsesInput Channels Skew One test pulse directly connected to each input channel Big skew between input channels (~1ns)- understood; Reason: differences in paths lengths on the PCB After fixing the paths lengths the skew should be reduced to ~0.4ns Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  42. Beam testsSnapshots, Clusters Size Distribution Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  43. Standard LB boxes VME crates Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  44. Safety of the DCS system • Problem of Single Point Failure effect • The “skip fault architecture” allows to limit SFP damage results to single Link Box • Amount of CCU chains – contradictory factors • To improve safety & throughput – should be as many chains as possible. • To keep the price reasonable – we should limit the number of CCU chains (less FEC boards and DOH modules). • Final decision should be taken after the prices of all components are known. Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  45. Solution of CCU related problems • The problems with too short read/write strobes in block mode have been confirmed • Special interface block will be needed to translate the “short” read/write accesses from CCU into “longer” read/write accesses on the Local Bus • The problem with CCU Alarms has been almost solved • Some minor problems with multiple alarms on the same line still exist – should be solved quickly Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  46. Time of “initial loading” of FLASHes • Theoretical limit: • 2 Mw(ords) in a single FLASH, 7μs typical time for programming of a single word. Thus, the programming of a single FLASH should take ci. 7 sec. • FLASHes may be programmed in parallel, but then the system throughput is a limiting factor • 2000 of FLASHes 1Mw each = 2GB of data • With effective throughput of 1MB/s in single chain we get ci. 2000 sec/number of chains Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  47. Time of FPGA refreshing • Main limiting factor – FLASH memory access time – ca. 100 ns • If we assume that the FLASH controller will be implemented in standard FPGA – FLASH controllers reconfiguration - ca. 15 ms • “User” FPGA reconfiguration – ca. 40-50 ms • Total 65 ms Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  48. Integration issues: position of LB boxes in the racks on the balconies L max= 11.5 m Cabling RE1/2 and 1/3 signalsLink Board Boxes (VME crates) in Racks Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  49. YE-1 Racks on Towers Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

  50. Barrel cabling S.Bally Jan Królikowski, CMS Annual Review, CERN Sept. 16, 2003

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