Wu, Jinyuan Fermilab Sept. 2012

1. A Digitization Scheme of Sub-uA Current Using a Commercial Comparator with Hysteresis and FPGA-based Wave Union TDC Wu, Jinyuan Fermilab Sept. 2012

2. Introduction • A current-to-frequency converting oscillator built with an ADCMP605+2R+C. • Small current input can be directly interfaced without pre-amplifier. • Variations of current are translated into output frequency. • FPGA Wave Union TDC with measurement resolution 25-30 ps can be used to measure times of comparator output logic transitions. A Sub-microampere Digitization Scheme

3. The Current to Frequency Converting Oscillator A Sub-microampere Digitization Scheme

4. The Current to Frequency Converting Oscillator Vout - + In HYS Vo+ Vo- - + In HYS • The input to the hysteresis causes variation to the high and low thresholds of the comparator. • The oscillation frequency changes accordingly. • The input waveform can be reconstructed from the logic transition times. A Sub-microampere Digitization Scheme

5. The Comparator Devices • ADCMP601 and ADCMP605 are comparators with hysteresis input. • Small variations of input current in HYS pin translated into hysteresis voltage changes. • The fully differential topology with ADCMP605 was used in our test. A Sub-microampere Digitization Scheme

6. The Input Current and the Output Frequency • When input current changes, out oscillating frequency deviating from nominal oscillating frequency. • The input amplitude used here is significantly larger than normal operation for demo purpose. A Sub-microampere Digitization Scheme

7. The Wave Union TDC Implemented in FPGA A Sub-microampere Digitization Scheme

8. TDC Using FPGA Logic Chain Delay • This scheme uses current FPGA technology  • Low cost chip family can be used. (e.g. EP2C8T144C6 $31.68)  • Fine TDC precision can be implemented in slow devices (e.g., 60 ps in a 400 MHz chip).  IN CLK A Sub-microampere Digitization Scheme

9. Two Major Issues In an FPGA TDC • Widths of bins are different and varies with supply voltage and temperature. • Some bins are ultra-wide due to LAB boundary crossing A Sub-microampere Digitization Scheme

10. Wave Union TDC records multiple transitions. Wave Union Launcher A Regular TDC records only one transition Wave Union Launcher A 0: Hold 1: Unleash In CLK A Sub-microampere Digitization Scheme

11. Wave Union Launcher A: 2 Measurements/hit 1: Unleash A Sub-microampere Digitization Scheme

12. Output Raw Data and Typical Delta T Histogram Between Two Channels 00003C C064A6 F064B8 C07CA4 F07CB4 C094A0 F094B0 C0AC9C F0ACAC C0C497 F0C4A8 C0DC91 F0DCA2 • RMS of this histogram is 25 ps. A Sub-microampere Digitization Scheme

13. Bench-top Tests A Sub-microampere Digitization Scheme

14. Test Hardware • An ADCMP605 + 2R, 1C are used to build a current controlled oscillator. • The output and oscillator network are fully differential. • Nominal sampling rate: 50-60 M samples/s. A Sub-microampere Digitization Scheme

15. Waveform Digitization Result • Times of oscillating transition edges are measured. • Both periods between positive and negative edges are calculated and their deviations from the nominal period are converted to current. • The input pulse is a single cycle sine wave with peak current 200 nA and base width 2x200 ns. • Charge movement of the pulse: +-200 nA x 200 ns x 0.64 = +- 25 fC. A Sub-microampere Digitization Scheme

16. Measurement Resolution • For DC input current, the oscillator timing jitters for transition edges are measured. • Pulse width RMS jitter: 280 ps. • Period RMS jitter: 470 ps. • The FPGA TDC’s with measurement resolution better than 25 ps fulfill the requirements easily. A Sub-microampere Digitization Scheme

17. Trade-off Between Sampling Rate and Resolutions • Consider time interval T(n) between edge 0 and edge n. • Sensitivity: DT(n)/DI ~ n • Timing jitter: s(T(n)) ~ sqrt(n) • Faster sampling rate: • Coarser s(I) • Finer s(Q) • Slower sampling rate: • Finer s(I) • Coarser s(Q) • The users can choose post process to suit their application. DI=250nA Dt=16ns DI=30nA Dt=1000ns A Sub-microampere Digitization Scheme

18. Resolutions and Sensitivities of Different Transitions 2us 2us • Each band of the M1 plot represents the transition time. • Vertical axis scale of M1: 2 us (the full scale of the left screen shot) • Slower sampling rates make current measurements with better resolutions. • FYI: M1 = CH1*AND(CH3>1.24,CH3<1.26) (Note: CH3 and CH4 50% level = 1.25V) A Sub-microampere Digitization Scheme

19. Performance of a Test • This is only a preliminary test. • Not every drop of oil is squeezed out. • Rooms for improvements and optimization are clearly available. • Colleagues are encouraged to try different configurations. A Sub-microampere Digitization Scheme

20. Open-Loop Gain vs. Deep Negative Feedback A Sub-microampere Digitization Scheme

21. Deep Negative Feedback - + • Analog electronics has been based on deep negative feedback. • We subconsciously apply deep negative feedback when we design analog circuits. • Amplification ability is traded-off for better gain stability, linearity and flat bandwidth. A Sub-microampere Digitization Scheme

22. ADC w/ Comparators: Taking Advantage of Open-Loop Gain - + Vout In • In digitization tasks, the primary requirement is to translate analog input into logic levels before it is contaminated by the noise. • All nonlinearity, gain variation etc. can be calibrated in digital domain. • In this example, the input voltage is compared with a known ramping reference voltage. • When reference voltage passes through the input level, the comparator amplifies the voltage difference with its open-loop gain. A Sub-microampere Digitization Scheme

23. A Collection of Examples A Sub-microampere Digitization Scheme

24. Ramp-Compare (Single Slope) ADC - + Vout In In+ Vo+ - + Vo- • The input voltage is compared with a known ramping reference voltage. • The input is sampled at fixed rate and the waveform can be reconstructed from the logic transition times of the comparator output. • Both single-ended and differential versions are available. • The FPGA LVDS input buffers can be used as the comparators and multi-channel ADC’s can be implemented with minimum external components. (4 resistors/CH for differential version.) In- 7-bit @ 62.5 MHz A Sub-microampere Digitization Scheme

25. The Duty Cycle Modulation Oscillator In Vout - + HYS • The pulse widths depend on the input voltage level. • The oscillator circuit is self-contained without external supports and is suitable for remote operation. A Sub-microampere Digitization Scheme

26. Time Over Threshold (TOT) - + In Vout • The leading edge time of the input pulse is accurately captured. • Pulse width is correlated with the pulse charge. • The FPGA LVDS input buffers can be used as the comparators. • Multi-channel T&Q measurements can be implemented in FPGA without external components. A Sub-microampere Digitization Scheme

27. Dynamic Time Over Threshold (DTOT, TODT) FF - + Vout In • The leading edge time of the input pulse is accurately captured. • The pulse width is nearly linearly correlated with total charge. • Better signal to noise ration (S/N) is anticipated. A Sub-microampere Digitization Scheme

28. Time Over Oscillating Threshold (TOOT) - + Vout HYS In • The leading edge time of the input pulse is accurately captured. • The circuit is simpler than TODT. • Multiple points are sampled on the pulse waveform. A Sub-microampere Digitization Scheme

29. Summary • Tests are performed with ADCMP605 oscillator. • Current measurement resolution of 47 nA (RMS) is achieved at 53 M sample/s, 6.5 nA (RMS) at 1 M samples/s is anticipated. • At 53 M samples/s, the product of 3-sigma current x sampling period is 2.7 fC. • Power consumptions for the oscillator and TDC are 37 mW and 27 mW/channel, respectively. A Sub-microampere Digitization Scheme

30. The End Thanks

31. Wave Union Launcher B Wave Union Launcher B 0: Hold 1: Oscillate In CLK A Sub-microampere Digitization Scheme

32. Cell Delay-Based TDC + Wave Union Launcher The wave union launcher creates multiple logic transitions after receiving a input logic step. The wave union launchers can be classified into two types: • Finite Step Response (FSR) • Infinite Step Response (ISR) This is similar as filter or other linear system classifications: • Finite Impulse Response (FIR) • Infinite Impulse Response (IIR) Wave Union Launcher In CLK A Sub-microampere Digitization Scheme

33. Wave Union Launcher A 0: Hold 1: Unleash In CLK A Sub-microampere Digitization Scheme

34. Wave Union? Photograph: Qi Ji, 2010 A Sub-microampere Digitization Scheme

35. A Current to Frequency Converter - + HYS - + HYS • The A Sub-microampere Digitization Scheme

36. Auto Calibration Using Histogram Method • It provides a bin-by-bin calibration at certain temperature. • It is a turn-key solution (bin in, ps out) • It is semi-continuous (auto update LUT every 16K events) 16K Events DNL Histogram S LUT In (bin) Out (ps) A Sub-microampere Digitization Scheme

37. Good, However • Auto calibration solved some problems  • However, it won’t eliminate the ultra-wide bins  A Sub-microampere Digitization Scheme

38. 1 2 Sub-dividing Ultra-wide Bins 1: Unleash Device: EP2C8T144C6 • Plain TDC: • Max. bin width: 160 ps. • Average bin width: 60 ps. • Wave Union TDC A: • Max. bin width: 65 ps. • Average bin width: 30 ps. 1 2 A Sub-microampere Digitization Scheme