Subnano Time to Digital Converter implemented in PARISROC for PMm² R&D program

1. CH0 Time - INL Ramp1 Cap2 Ramp1 & Ramp2 reconstruction Ramp Noise 1.6 2.5 750 Noise.Cap1.Ramp1 Noise.Cap2.Ramp1 700 2 1.4 650 1.5 1.2 600 1 1 550 0.5 ADC Channel ADC Channel 0.8 500 ADC Channel 0 450 0.6 -0.5 400 0.4 -1 350 0.2 Hold -1.5 300 0 0 50 100 150 200 250 300 350 400 -2 120 130 140 150 160 170 180 190 200 210 Time in ns Ramp Time in ns -2.5 TDC1 0 10 20 30 40 50 60 70 80 90 100 Read Time in ns 4 StartRamp x 10 2 1.8 Ramp TDC2 1.6 1.4 1.2 Select good TDC SC 1 stored 0.8 Select good TDC D Q Delay 0.6 Hold 0.4 Rst 0.2 0 99.9375 99.938 99.9385 99.939 99.9395 99.940 99.9405 99.941 99.9415 LAPP Annecy: IN2P3-CNRS-Université de Haute Savoie http://lappweb.in2p3.fr D. Duchesneau, N. Dumont-Dayot, J. Favier, R. Hermel, J.Tassan-Viol, A. Zghiche IPN Orsay: IN2P3-CNRS-Université Paris Sud 11 http://ipnweb.in2p3.fr S. Drouet, B. Genolini, B.Y. Ky, T. Nguyen Trung, J.Peyré, J. Pouthas, P. Rosier, E.Wanlin Topical Workshop on Electronics for Particle Physics 2010— Aachen, Germany, 20-24 September, 2010 Reset CMOS http://pmm2.in2p3.fr C=500fF S. Drouet on behalf of the PMm2 collaboration Load 32 T&H cells Vref Vslope • PARISROC • PARISROC_v2 is a dedicated front-end ASIC for photomultiplier tubes designed by LAL/OMEGA group and by IPNO for the analog TDC. • AMS SiGe0.35µm, size: 5 mm x 3.4 mm • 16 independent channels • Independent gain adjustment • by channel • Charge and time digitization • Serial readout @ 40 MHz • Charge: 0 to 300x106 electrons • Efficiency from 106 e- input charge • Virtual 12-bit ADC @ 40 MHz • (10-bit Wilkinson ADC + 2 gains with automatic selection) • Time measurement: • Analog TDC: Dyn. = 100 ns, step 220 ps, resolution 425 ps RMS • Digital TDC: Dyn. = 1.67 s, step 100 ns (24 bits / 10 MHz) • TDC Ramp Generator • Architecture: a simple current source and an integrator. • Loads: 16 channels 32 T&H cellswithindependent • switching (1 T&H = 500 fF) • Load variation: from 0 to 16 pF on eachrampgenerator • Constraint: Charge variation do not have to perturb • the linear zone of a ramp • RampSlope: 10 mV / ns • RampDynamic: 1.4 V / 140 ns • Usable RampDynamic: 1 V / 100 ns • Target resolution: 100 ps NMOS I=5µA R=200kΩ Ramp Slope = 5 µA / 500 fF = 10 mV / ns BandgapprovidesVref and Vslope Integrators Mirror sources PARISROC Layout MUX MUX OR StartRamp One RampGeneratorSchema • Special Cares • Design: • Ramp generatorlinearity • Charge injection in memorycells: Optimization of switchsizes • Immunity of a cell relative to switchingneighbourcells • Layout: • Centroid layout for the amplifier input pairs • Mirroring of the 2 TDC rampgenerators • Dedicated power supplies • The goal of thesespecial cares is to minimizemismatching and obtain the samecharateristics on eachramp. And as the rampswork in opposition phase, the reset zone of one ramp must have the lowest possible impact on the other. Time constant (3bits) Gain Correction (8bits) Subnano Time to Digital Converter implemented in PARISROC for PMm² R&D program CRRC2 Slow Shaper (25 , 50, 100 ns) Variable Gain Pre-Amplifier (0.25-4) Low Gain Depth 2 SCA Low Gain 16 Inputs Discri CRRC2 Slow Shaper (25 , 50, 100 ns) Depth 2 SCA High Gain Variable Gain Pre-Amplifier (2.5-40) High Gain Gain Selection Hold 10 bits DAC Variable Delay 6 bits Fast Shaper (15ns) Discri Trigger Output 10 bits DAC Ramp Selection Optimisation External Trigger Depth 2 SCA Fine Time TDC Ramp 1 Common to 16 channels TDC Ramp 2 Depth 2 SCA Fine Time Synoptic of PARISROC ASIC INL<0.1 % FS (<100 ps) for 134 ns over 140 ns ramp StartRampTDCfrom digital part Analog TDC Principle 2 rampsworking in phase opposition withoverlap zones. When one is in the reset zone, the otheris in the linear zone. Therefore, the time measurementis possible withoutblind zone because, at least, always one of the tworampsis in a linear zone. A digital module, implemented in eachchannel, selects the valid TDC ramp. Whenan eventoccurs, the 2 ramps are sampledat the same time in the Track&Holdcells and a logic module tags the valid one. Only the sample of the selectedrampisconverted. RampTDC 1 RampTDC 2 Reset zone Non-linear zones SelectTDC StartRampTDCdelayed Usable Ramp (Virtual view) Digital part 24 bits Timestamp Counter 10MHz Wilkinson 10 Bits ADC 40MHz Serial data 51 bits 140ns Read-out 40MHz 4bits Channel 24b Timestamp 1b Counter 1b Gain 10b Fine Time 1b Ramp 10b Charge Slow Control SCA management Tests and Results Ramps reconstruction, noise and INL measurements: Mean of 10 000 data each nsMax.Noise = 322 ps RMSINL = 2 ch 450 ps Time measurementof 10 kHz signal Visualization of Ramps with oscilloscope 1V 100ns FunctionnalChronograms Dual-RampGeneratorLayout Reset impact of Ramp2 Discriminator 1 channel Event Track & Hold X2 Multiplexor CH0 Time Measurement To ADC WithTimeStamp and Ramp Corrections Mean = 99939.340 ns Std = 425.00 ps Track & Hold X2 Injection: Periodical signal = 100 µs Count Principle Time in µs ANR-06-BLAN-0186 Université Libre de Bruxelles http://www.ulb.ac.be K. Hanson LAL Orsay: IN2P3-CNRS-Université Paris Sud 11 http://www.lal.in2p3.fr J.-E. Campagne, S.Conforti, F.Dulucq, M. El Berni C. de La Taille, G. Martin-Chassard