Multi-Project Reticle Floorplanning and Wafer Dicing

Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng1 Ion I. Mandoiu2 Qinke Wang1 Xu Xu1 Alex Zelikovsky3 (1)CSE Department, University of California at San Diego (2) CSE Department, University of Connecticut (3) CS Department, Georgia State University

Outline Introduction to Multi-Project Wafer Design flow Side-to-side wafer dicing problem Reticle floorplanning and wafer dicing problem Experimental results Conclusions and future research directions

Mask and Wafer Cost Mask cost: $1M for 90 nm technology Wafer cost: $4K per wafer

Introduction to Multi-Project Wafer Share rising costs of mask tooling between multiple prototype and low production volume designs  Multi-Project Wafer Image courtesy of CMP and EuroPractice

History of Multi-Project Wafer Introduced in late 1970s and early 1980s Companies: MOSIS, CMP, TSMC Several approaches proposed Chen et al. give bottom-left fill algorithm, 2003 Anderson et al. proposed grid packing algorithm, 2003 Tools: MaskCompose, GTMuch

Design Flow • Unique designs

Design Flow • Custom designs • Partition between reticles

Design Flow • Custom designs • Partition between shuttles • Reticle placement

Design Flow • Custom designs • Partition between shuttles • Reticle placement • Stepper shot-map shot-map print

Design Flow • Custom designs • Partition between shuttles • Reticle placement • Stepper shot-map • Dicing plan design

Design Flow • Custom designs • Partition between shuttles • Reticle placement • Stepper shot-map • Dicing plan design • Extract dice

Why Dicing a Problem? Side-to-side dicing is the prevalent wafer dicing technology Sliced out A die issliced outif and only if: • Four edges are on the cut lines • No cut lines pass through the die Dicing iscomplex for MPW. Most dice will be destroyed if placement is not well aligned. Dicing iseasy for standard wafers. All dice will be sliced out.

Side-to-side Dicing Problem Given: • reticle placement • wafer shot-map • required volume for each die Find: • Set of horizontal and vertical cut lines (dicing plan) To Minimize: • w = # wafers used

H-Conflict 2 1 3 4 2 2 2 1 1 1 3 4 3 4 3 4 dice are in H-Conflict if they can not be sliced out horizontally. 1 and 2 are in H-conflict Die 1 is in H-Conflict with entire row of Die 2.

Horizontal Dicing Plan 2 2 2 1 1 1 3 3 3 4 4 4 • A horizontal Dicing Plan (DP) is a set of lines which dice one • row of prints • A set of dice which are pairwise not in H-conflict can be • sliced out by a DP • We seek such maximal horizontal independent sets The dicing plan which slices out dice 1 and 4 MHIS (MVIS) = set of all horizontal (vertical) DPs

Interval Coloring 2 2 1 1 3 3 4 4 • Two dice are in H-conflict iff their vertical projections overlap •  Interval graph, which can be optimally colored • All dice of the same color can be horizontally sliced out 2 1 1 2 3 4 3 4 2 1 3 4

Non-Linear Programming Formulation • Assume the wafer is a rectangular array of prints. • fH= # rows (with DP H) one DP per row = # rows whose dicing plans slice out Di

Non-Linear Programming Formulation • Assume the wafer is a rectangular array of prints. • gV= # columns (with DP V) one DP per column = # columns whose dicing plans slice out Di

Non-Linear Programming Formulation N(Di)= # required copies of die Di z=1/(# wafer) Must slice out at least the required volume copies sliced out

Non-Linear Programming Formulation • Assume the wafer is a rectangular array of prints. • fH= # rows (with DP H) • gV= # columns (with DP V) • N(Di)= # required copies of die Di Maximize: z = 1/(# wafers) Subject to:

Integer Linear Programming Formulation One DP per row

Integer Linear Programming Formulation One DP per column

Integer Linear Programming Formulation The print at rth row and cth column is diced by DP H and V iff we use H at the rth row and V at the cth column

Integer Linear Programming Formulation Di sliced out otherwise Sliced out at least required volume

Integer Linear Programming Formulation Maximize: z = 1/(# wafers) Subject to:

Iterative Augment and Search Algorithm (IASA) DP1 • Choose initial dicing plan using interval graph coloring DP2

Iterative Augment and Search Algorithm (IASA) DP1 • Choose initial dicing plan using interval graph coloring • In each iteration, first check whether z will increase by changing the dicing plan for one row or column DP1,…,DP|MHIS| DP2 DP1,…,DP|MVIS|

Iterative Augment and Search Algorithm (IASA) • Choose initial dicing plan using interval graph coloring • In each iteration, first check whether z will increase by changing the dicing plan for one row or column • Choose one dicing plan for one new row or column which maximizes z DP1 DP3 DP1,…,DP|MHIS| DP2

Experiment Setup • Ten random testcases with different numbers of dice • Required production volume is 40 for all dice • Assume a wafer has 10 rows and 10 columns of prints • We used CPLEX 8.100 to solve LP • We used LINGO 6.0 to solve NLP • We implemented the IASA heuristic in C • All tests are run on an Intel Xeon 2.4GHz CPU

Experimental Results for SSDP • Performance of IASA is much better

What Floorplan is Good? • Min-area floorplan •  high wafer cost 1 2 1 2 1 2 3 3 4 4 3 4 1 2 1 2 40 wafers needed for 40 copies 3 3 4 4

What Floorplan is Good? • Min-area floorplan •  High wafer cost 1 2 1 2 1 2 3 3 4 4 3 4 1 2 1 2 40 wafers needed for 40 copies 3 3 4 4 • Diagonal floorplan • Larger reticle • High wafer cost 4 2 1 3

What Floorplan is Good? 2 1 4 3 • Min-area floorplan •  high wafer cost 1 2 1 2 1 2 3 3 4 4 3 4 1 2 1 2 40 wafers needed for 40 copies 3 3 4 4 • Diagonal floorplan •  high mask cost 4 2 1 3 2 2 1 1 4 3 4 3 • Good floorplan 2 2 1 1 4 3 4 3 20 wafers needed for 40 copies

Reticle Design and Wafer Dicing Problem • Given: n dice Di (i=1…n), • reticle size • Find: • placement of dice within the reticle • and a dicing plan • To Minimize: • w, the number of wafers used

Shelf Packing and Shifting • Sort dice according to height

Shelf Packing and Shifting • Sort dice according to height • For all possible shelf widths, insert the dice into the shelves

Shelf Packing and Shifting • Sort dice according to height • For all possible shelf widths, insert the dice into the shelves • Shift the dice to align them with the dice on other shelves and calculate z using IASA

Shelf Packing and Shifting • Sort dice according to height • For all possible shelf widths, insert the dice into the shelves • Shift the dice to align them with the dice on other shelves and calculate z using IASA • Choose the placement with the max z

Simulated Annealing Placement • Get a shelf packing floorplan as the initial floorplan • Calculate Objective Value =(1-α) area+ α(100-z) • While (not converge and # of move < Move_Limit) • { • choose a uniform random number r • make a random move according to r • calculate δ= New Objective Value - Old Objective value • If (δ <0) • Accept the move • Else • Accept the move with probability exp(- (δ/T)) • T=β T • }

Experimental Results for RDWDP • GTMuch is a commercial tool for MPW • Improve wafer yield z by 37.7% compared with GTMuch • Improve wafer yield z by 30.5% compared with shelf+shift

Solutions for Testcase 1 GTMuch Parquet Shelf+shift Simulated annealing

Conclusions We presented a MPW design flow We propose practical mathematical programming formulations and efficient heuristics, which can be extended to the case when margins are allowed The shelf packing and shifting algorithm can improve yield by 37.7% while reducing reticle area by 3.3% compared to GTMuch. By using the simulated annealing code, we can further improve wafer-dicing yield by 30.5% at the expense of an increase of area by 3.3%.

Future Research Validate proposed methods on industry testcases Extend the proposed algorithms to round wafer Multiple dicing plans

Thank you for your attention!

Multi-Project Reticle Floorplanning and Wafer Dicing