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This study focuses on bus-driven floorplanning, emphasizing multi-bend buses and efficient shape validation methods for optimal chip area utilization. The methodology involves sequence pair analysis, bus ordering, and floorplan realization to achieve minimized bus area and chip area. Experimental results validate the approach's effectiveness.
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Multi-Bend Bus-Driven Floorplanning Jill H.Y.Law & Evangeline F.Y.Young The Chinese University of Hong Kong
Outline • Introduction • Background • Sequence Pair • Methodology • Shape Validation • Bus Ordering • Floorplan Realization • Experimental Results • Conclusion
Background • Why is bus-driven floorplanning important? • Previous work: • Hua Xiang, Xiaoping Tang and Martin D.F. Wong “Bus-Driven Floorplanning” ICCAD 2003 • 0-bend is not enough for buses going through many blocks
Problem Formulation • A set of n blocks B = {b0, b1, …, bn-1} • A set of m buses U = {u0, u1, …, um-1}, where each bus is associated with a width ti • Decide the position of blocks, such that • Buses go through their blocks • Chip area minimized • Bus area minimized • Buses can have at most 2-bends
Problem Formulation • What is meant by “going through” ? • Assume block height > bus width
Sequence Pair (SP) • A pair of sequences of n elements • (…a…b…, …a…b…), a is on the left of b • (…a…b…, …b…a…), a is on top of b • Example: (acbde, daceb)
Overview • While Temp > threshold • Apply a move to obtain a new SP • Evaluate the floorplan • Shape Validation • Bus Ordering • Floorplan Realization • Accept or reject according to Cost and Temp
Steps • Assumption • 2 layers for bus routing • Evaluation • Shape Validation • 0-bend • 1-bend • 2-bend • Bus Ordering • Floorplan Realization
Shape Validation • Check the bus one by one • From the relative position of the blocks, check if a bus of at most 2 bends can go through all blocks
Shape Validation – 0 bend • Step 1: Extract the related blocks from the sequence pair • Example: For a bus ABE • Given a SP (ABCDE, ABCED) (ABE, ABE) • Step 2: Check relative position between blocks • Example: For a bus ABC • Horizontal bus: (ABCDE, ADEBC) (ABC, ABC) • Vertical bus: (CDBEA , ABCDE) (CBA, ABC)
Shape Validation – 1 bend • L-shape bus • 1 horizontal component • 1 vertical component • How to recognize them? • Step 1: Extract the related blocks (X, Y) • Step 2: Find the Longest Common Subsequence (LCS) of (X, Y) Horizontal component
Shape Validation – 1 bend • Step 3: Check if the remaining blocks in reverse order • Example: (ABCDEF, ABCFED) • LCSABCD, remaining blocks (DEF, FED) • Step 4: Check if T-shape • T-shape also contains one horizontal component and one vertical component • T-shape is kept for later 2-bend checking
Shape Validation – 1 bend • When will a T-shape be formed?
Shape Validation – 1 bend • Example: (ABCDE, ADCBE) • Horizontal Component: ABE • Vertical Component: CD
Shape Validation – 2 bend • C-Shapes, Z-Shapes, mirrored Z-Shapes … • HVH or VHV • Assume HVH (VHV is similar) • How to recognize them? • Step 1: Extract the related blocks (X, Y) • Step 2: Find the LCS of (X, YR) vertical • Example: (ABCDE, ADCBE) • Find the LCS of (ABCDE, EBCDA): BCD
E A B C D Shape Validation – 2 bend • Step 3: Put the remaining blocks in different relationships with the vertical component
Shape Validation – 2 bend • 8 possible relationships • Step 4: Put the blocks into 2 horizontal components
Shape Validation – 2 bend • Example: (GHABCEFD, EFDCBGHA) • (GHABCEFD, AHGBCDFE) vertical component • Upper = {A, H, G}, Lower = {D, E, F} • A C-shape can be formed
Shape Validation – 2 bend • Example: (AEBCDF, EDCBFA) • (AEBCDF, AFBCDE) vertical component • Upper = {A}, Lower = {D}, LowerLeft = {E}, LowerRight = {F} • No valid 2-bend shape can be formed
Shape Validation • Extract the related blocks • Check if 0-bend • Check if 1-bend • Assume HVH • Check if 2-bend • Assume VHV • Check if 2-bend • Mark it invalid if all “no”
Steps • Evaluation • Shape Validation • Bus Ordering • Floorplan Realization
Bus Ordering • Step 1: Split all the buses into 0-bend bus components • Step 2: Build vertical graph and horizontal graph by looking at each pair of bus components • Use a node to represent each bus component • If bus component a has to be on top of bus component b, add an edge from node a to node b • If there is cycle, at least one bus component in the cycle has to be removed • Horizontal graph can be built in a similar fashion
Bus Ordering • Step 3: If there are cycles, remove nodes (bus components) to make the graph acyclic • Aim at removing the least number of nodes • NP-complete • Maximum degree heuristic • Step 4: Remove the corresponding bus components in the other graph as well
Steps • Evaluation • Shape Validation • Bus Ordering • Floorplan Realization
Floorplan Realization • Realization = obtaining the positions of the blocks and buses • This step is the same as that in Xiang’s work
Simulated Annealing • Simulated Annealing Framework • Moves: • Swap • Rotation • Cost Function • Cost = ‧A + ‧B + ‧I • A: chip area, B: total bus area, I: number of invalid bus • Can consider other aspects by adding more terms in the cost function • Total wire length • Routing congestion
Summary • While Temp > threshold • Apply a move to obtain a new floorplan • Evaluate the floorplan • Shape Validation • Bus Ordering • Floorplan Realization • Accept or reject according to Cost and Temp
Platform • Language • Implemented using C ++ • Machine • Intel Xeon (2.2 GHz) with 1 G memory • MCNC benchmarks
Experimental Results • The data set used in Xiang’s work * calculated by [(y1 – y0) / y0]*100%
Experimental Results • In this data set, each bus has to go through 10 – 15 blocks * calculated by [(y1 – y0) / y0]*100%
Experimental Results • ami49 – 2
Experimental Results • ami49 – 3
Experimental Results • ami49 – 6
Conclusion • Solve the bus-driven floorplanning problem for 0-bend, 1-bend, 2-bend buses • The presence of 1-bend and 2-bend buses is important, especially when the number of blocks that a bus goes through is large