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Verilog Tutorial 3

Verilog Tutorial 3. Jack Ou , Ph.D. CES522 Engineering Science Sonoma State University. Outline. Motivation Blocking Assignments Non-Blocking Assignments. Shift Register Using Blocking Assignments. Te st Bench for the Shift Register . Clock cycle: 10 intervals

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Verilog Tutorial 3

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  1. Verilog Tutorial 3 Jack Ou, Ph.D. CES522 Engineering Science Sonoma State University

  2. Outline • Motivation • Blocking Assignments • Non-Blocking Assignments

  3. Shift Register Using Blocking Assignments

  4. Test Bench for the Shift Register • Clock cycle: 10 intervals • Input (E) changes state Every 40 intervals

  5. Output E is updated every 40 cycles A is updated 30 intervals after E

  6. A=Delayed E

  7. Reverse Update Algorithm

  8. = • The assignment operator (=) causes statements to be executed in the listed order, with the storing of value occurring immediately after any statement can executed and before the next statement. • Order matter!!! • = is used with blocked statements.

  9. <= • Nonblocking assignments are made with the nonblocking assignment operator (<=)instead of the assignment operator. Nonblocking assignment statements effectively execute concurrently ( in parallel) rather than sequentially, so the order in which they are listed has no effect.

  10. Shift Register using <=

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