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Verilog XL Tutorial

Verilog XL Tutorial. By Greg Edmiston Scott McClure August 2004. Tutorial Disclaimer.

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Verilog XL Tutorial

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  1. Verilog XL Tutorial By Greg Edmiston Scott McClure August 2004

  2. Tutorial Disclaimer • This tutorial includes one way of simulating in Verilog XL. This is not necessarily the best way of simulating, depending on your requirements. This tutorial is a simple step-through designed to familiarize the user with Verilog XL, and thus is basic in nature. More advance simulations are not found in this tutorial.

  3. Create Verilog File • Create a text file with the text shown here • This code represents a basic circuit with delay and test stimulus • Save as “example.v” • Verilog code files often have a “.v” file extension

  4. Enter ICFB • Type “who am i” • Gives xhost address • setenv DISPLAY {xhost} • Type “icfb &” to start Cadence

  5. Import Verilog File in ICFB • Import the “example.v” Verilog file by choosing File >> Import >> Verilog in ICFB CIW

  6. Importing Verilog File • “Verilog In” window pops up • Set Target Library Name to “new” • Highlight “example.v” in file selection box at the top of the window • Press the Add button on the “Verilog Files to Import” line • Click OK at the top of the “Verilog In” window

  7. Verify File Import • Open up the Library Manger from the CIW and inspect to ensure the “new” library includes a cell named “circuit_with_delay”

  8. Verify File Import • Open the Schematic view of the “circuit_with_delay” from the Library Manager and verify that it resembles the screenshot to the left

  9. Running Verilog XL • Close all windows except a terminal • From your home directory type “verilog +gui example.v” • Verilog should open with your example loaded • Note: “example.v” has to be saved in your home directory for this command to function

  10. Simulating with Verilog XL • Verilog should open the SimVision Design Browser and Console • The stimcrct module should be displayed under the simulator icon

  11. Simulating with Verilog XL • Click on the stimcrct icon • The circuit inputs and outputs should now be visible under Signal/Variable

  12. Simulating with Verilog • With the stimcrct highlighted choose Select>>Signals

  13. Simulating with Verilog XL • Now that the signals are highlighted, send them to the logic display by clicking on the indicated button Click Here

  14. Simulating with Verilog XL • Click the Play button to run the simulation Run Button

  15. Simulating with Verilog XL • Since the simulation has no initial stop point the output will appear similar to the window to the left

  16. Simulating with Verilog XL • To rerun the simulation it must first be reset • Reset the simulation by choosing “Reinvoke Simulator” from the simulation menu

  17. Simulation with Verilog XL • Run the simulation by pressing the Run button Run Button

  18. Simulation with Verilog XL • Simulation output should look like this

  19. Conclusion • This concludes the Verilog XL Tutorial • This tutorial was derived from the SMU Cadence Verilog XL Tutorial • http://engr.smu.edu/~mitch/class/3381/verilog_intro.pdf

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