Verilog Tutorial

Verilog Tutorial Chin-Lung Su （蘇錦榮） Laboratory for Reliable Computing (LaRC) Electrical Engineering Department National Tsing Hua University

Outline • Introduction • Combinational Circuit • Programming style • How to program • Test-bench

Introduction • Hardware Description Language (HDL) • Verilog is useful and popular language • Parallel not serial (Not like C language) • Meaningful declaration • parameter, port name, module name, … • Identifies • “Even” and “even” are different

Structure Programming

Module • Module is a block of circuit • Special function • and, or, mux, adder, … • Most important • Input and Output Module

Flow • What functions are you want to program ? • Input and output • Separate the whole circuit into smaller ones • Each block has its own function / purpose B1 B2 B3

Scenario Stimulus & Control Signal Response & Verification Test-Bench Module Monitor Signals

Verilog Model

Module Declaration • module module_name(input1, input2, …, output1, output2, …) • Example • module mux2(a, b, c); • module adder(x, y, z); endmodule

Datatypes • Nests • Wire • C[1:0] = {a,b} • Registers • reg • Integers • 4’d3, 4’b0100, 6’h20 • Array • reg [9:0] ram • Parameter • parameter word_size = 16 • wire [word_size-1:0] bus; • Preprocessor Directive • `define BEQ 4’b0100 No “=”

Synthesizable Description

Un-synthesizable Description

Synthesizable Operator • Binary Bitwise operator • ~ inverse • & and • | or • ^ XOR • ~^ XNOR • Example • Assign a=~b; if b = 4’b0010; then a = 4’b1101;

y z 0 1 x y z 1 0 0 0 0 0 1 0 1 0 0 1 1 1 x y z 0 0 0 0 1 1 1 0 1 1 1 1 Logic x y x x z z y y

Example • assign a=b & c • assgin a=b | c b = 4’b0011 c = 4’b0101 a = 4’b0001 b = 4’b0011 c = 4’b0101 a = 4’b0111

a + Mux s - b op Program 1 • Purpose • A circuit can calculate the addition and subtraction of two 8 bits numbers • Three inputs and one output

Program 1 (cont.) /* A first program in Verilog */ module adder_or_subtract( a, b, op, s); parameter SIZE = 8; parameter ADD = 1’b1; input op; input [SIZE-1:0] a,b; output [SIZE-1:0] s; wire add, sub; assign add = a+b; assign sub = a-b; assign s = (op==ADD)? add : sub; endmodule comment Model declaration add a + Mux s - sub b op

Program 1 (cont.) module adder_or_subtract( a, b, op, s); parameter SIZE = 8; parameter ADD = 1’b1; input op; input [SIZE-1:0] a,b; output [SIZE-1:0] s; assign s = (op==ADD)? A+b : a-b; endmodule

D y0 y0 z1 Select 0 D 0 y1 1 0 D Select Program 2 • 1-to-2 De-multiplexer

Program 2 (cont.) /* A deMux program in Verilog */ module demux ( D, select, y0, y1); input D; input select; output y0,y1; wire y0,y1; assign y0 = (~select) & D; assign y1 = select & D; endmodule comment Model declaration

B1 B2 B3 Sub Module • Complex circuit • Many modules in a circuit • Module, sub-module, sub-sub-module, …

B1 B2 B3 Example of Call Module • module B1(a, b, c); ……………….. • endmodule • module B2(a, b, c, d); ……………….. • endmodule • module B3(x, y, z); ……………….. • endmodule

Example of Call Module (cont.) • module function(q, w, e, f); • ……. • B1 b1(q, w, a, b, c); • B2 b2(a, b, d, e); • B3 b3(c, d, f); • …… • endmodule • module B1(a, b, c); ……………….. • endmodule • module B2(a, b, c, d); ……………….. • endmodule • module B3(x, y, z); ……………….. • endmodule

B1 w q c q w f a e Port Mapping Between Modules • # of ports need the same • Width of each port needs the same • module function(a,b,c,d); • ……. • B1 b1(w, q, a, c); • endmodule • module B1(q, w, e, f); • input q, w; • input [3:0] e; • output [1:0] f; • ………………. • endmodule

Port Mapping Between Modules (cont.) • Port name should match the name in sub_module • Prot connection • module_name( .port1_m1(w1_or_r1), .port2_m1(w2_or_r2), .port3_m1(w3_or_r3), .port4_m1(w4_or_r4), ) • module_name( .port3_m1(w3_or_r3), .port2_m1(w2_or_r2), .port1_m1(w1_or_r1), .port4_m1(w4_or_r4), )

Connection Between Modules (cont.) • Prot connection B1 q q • module function(a,b,c,d); • B1 b1(q, w, a, c); • B1 b1(.q(q), .w(w), .e(a), .f(c)) • B1 b1(.w(w), .q(q), .e(a), .f(c)) • endmodule c w w f a e • module B1(q, w, e, f); • input q, w; • input [3:0] e; • output [1:0] f; • ………………. • endmodule

Reuse Module • Using the same module many times • Example • Constructing 4-bits adder with four 1-bit adder b3 a3 b2 a2 b1 a1 b0 a0 A A A A c3 c2 c1 0 s4 s3 s2 s1 s0

4-bists Adder • module Adder(x, y, cin, sum, cout); • input x, y, c; • output sum, cout; • wire x, y, c, sum, cout; • assign sum = x ^ y ^ cin; • assign cout = (x & y) | (x & cin) | (y & cin); • assign {cout, sum} = x + y + cin; • endmodule y x A cout cin sum

4-bists Adder (cont.) b3 a3 b2 a2 b1 a1 b0 a0 • module Adder4(x, y, cin, sum); • input [3:0]x, y • input cin; • output [4:0]sum; • wire [3:0] x, y; wire cin; • wire [4:0] sum; • wire c1, c2, c3; • Adder A1(x[0], y[0], cin, sum[0], c1); • Adder A2(x[1], y[1], c1, sum[1], c2); • Adder A3(x[2], y[2], c2, sum[2], c3); • Adder A4(x[3], y[3], c3, sum[3], sum[4]); • endmodule A A A A cin c3 c2 c1 s3 s2 s1 s0 s4

Mistake • module and endmodule • module();而不是Module(); • 每一行漏加分號(;) • port 數目及bus寬度不對

Always Block • Syntax • always @(event-expression) assignment or block • Level type • always @(a or b or c) • Edge type • always @(posedge clock) • always @(negedge clock) • if-else and case statement are only in always block • wire and reg

Example • wire a; • reg b; • always @(x or y or z) • begin • a <= x & y; • b <= x | z; • end error correct

D y0 y1 Select Program 2 (cont.) /* A deMux program in Verilog */ module demux ( D, select, y0, y1); input D, select; output y0,y1; reg y0,y1; always @( D or select ) begin if( select == 1’b0)begin y0 = D; y1 = 1’b0; end else begin y0 = 1’b0; y1 = D; end end endmodule

Blocking and Non-blocking • Symbol • Blocking “ = ” • Non-blocking “<=” A = B B = A A <= B B <= A A A B B

Blocking and Non-blocking

if statement • Like C language • Only in always block reg out; always @(sel or a or b) begin if(sel == 1’b1) out = a; else out = b; end wire out; assign out = (sel)? a : b;

Using of case and casex • Multiplexer or selection • Inside always block • All possible condition always @(sel or a or b or c or d) begin case (sel[1:0] ) 2’b00 : out <= a; 2’b01 : out <= b; 2’b10 : out <= c; 2’b11 : out <= d; endcase end a b out c d Sel [1:0]

a b out c Sel [1:0] a b out c d Sel [2:0] Using of case and casex (cont.) always @(sel or a or b or c or d) begin case (sel[1:0] ) 2’b00, 2’b11 : out <= a; 2’b01 : out <= b; 2’b10 : out <= c; endcase end always @(sel or a or b or c or d) begin casex (sel[2:0] ) 3’b011 : out <= a; 3’b00x : out <= b; 3’b100 : out <= c; default : out <= d; endcasex end All others

Delay and Critical Path • Each gate and wire may cause delay of circuit • Longest path of the circuit is critical path • Speed of whole circuit • Shorten the critical path can speedup the circuit • Input data rate higher than the speed of circuit may cause some problems

a b c d + + + e + Z Critical Path Example • 5 inputs adder • Z = a + b + c + d + e Z = (a + b) + (c + d) + e a b + c + d Four adders Three adders + e + Z

Test-bench • Input data of the circuit • All inputs of original circuit are assigned “reg” • Store data • All outputs of original circuit are assigned “wire” • Assign inputs in different time • Define time scale

Test-bench Example • `timescale 1ns/100fs • module Adder_testbench; • reg [3:0] x,y; reg cin; wire [4:0] sum; • adder4 add(.x(x), .y(y), .cin(cin), .sum(sum)); • initial begin • #0 x = 4’d0; y = 4’d0; cin=1’b0; • #10 x = 4’d3; • # 5 y = 4’d10; • #10 x = 4’d1; y = 4’d5; • end • endmodule Initialization In 10ns x=3; y=0; sum=3; In 25ns x=1; y=5; sum=6; In 15ns x=3; y=10; sum=13; module Adder4(x, y, cin, sum);

Verilog Tutorial