2013 CAD Contest at ICCAD

1. 2013 CADContest at ICCAD Technology Mapping for Macro Blocks Team: Cix Member: Chih-Chung, Wan-Chen, Chia-Yao, Ching-Shen

2. outline • Mapping constrain in ABC • Idea: map with supergate • Difficulties • Future work

3. Mapping constrain in ABC • Map • performs standard cell mapping of the current network using current library. • Library format: GENLIB.

4. Mapping constrain in ABC • GENLIB:

5. Mapping constrain in ABC • GENLIB: Cell name Cell logic function Cell area

6. Mapping constrain in ABC • GENLIB: delay Pin name Input load Phase Max load

7. Mapping constrain in ABC • GENLIB: “ ! ” or “ ‘ ” = NOT “ * ” = AND “ + ” = OR

8. Map with supergate • Super • Generates supergates for the given standard cell library. • A GENLIB library should be given.

9. Map with supergate • Idea • See modules (given by the contest host) as supergates. • Transform Verilog to GENLIB.

10. Difficulties • GENLIB needs more information than Verilog. • Arithmetic functions are not defined by GENLIB.

11. Future work • Try to implement the idea and evaluate feasibility.