2013 CAD Contest Technology Mapping for Macro Blocks

1. 2013 CAD Contest Technology Mapping for Macro Blocks Team: WCYLab-Bach Ching-Yi Huang, Wei-An Ji, Yu-Min Chou, Zheng-Shan Yu Date: 2013/7/22

2. Outline • Problem Formulation • Framework & Flow • Logical macro mapping • Continuous AND/NAND/OR/NOR/XOR/XNOR • Arithmetical macro mapping • Adder • Others • Framework • Cutting • Matching • Progress & Future Work

3. Problem Formulation

4. Framework (I/O) ABC D D.blif Mapping ABC D’.blif D’.v Library VTR L.blif

5. design.v lib.v Verilog Parser blif AIG Resyn2 Optimize NMG+NAR Yes 1. node# decrease? Continuous AND OR map No Algorithm 3. 2. K cut Lazy man Adder Output Standard cell mapping Out.v

6. Framework & Flow • Classify the libraries into two categories • For logical macro blocks • Search for continuous AND/NAND/OR/NOR • Search for continuous XOR/XNOR • For arithmetic macro blocks • Adders • Others • Partition the multi-PO circuit into single-PO TFICs • Only deal with the K-cuts sub-circuits, where K < 13 • Map the cuts using Lazy Man’s method • Greedily cut & match the macros • Standard cell technology mapping • Transform the AIG to the normal gate-level circuit • Isolate the mapped macro blocks at the same time

8. Outline • Problem Formulation • Framework & Flow • Logical macro mapping • Continuous AND/NAND/OR/NOR/XOR/XNOR • Arithmetical macro mapping • Adder • Others • Framework • Cutting • Matching • Progress & Future Work

9. Continuous AND Gates • Use DFS and Disjoint Set to do the searching in the netlist • Consider • No fanout in the cone • Maximum input number of the macro PI-1 DFS Target PI-2

10. Continuous NAND/OR/NOR Gates • Use DFS and Disjoint Set to do the searching in the netlist • Consider the locations of inverters Cont. NAND Cont. OR Cont. NOR Target Target Target PI-1

11. Issue • Fanout-reconverge Target

12. Issue • Fanout-reconverge Target

13. Issue • Fanout-reconverge Target

14. Issue • Fanout-reconverge PI-1 Target n1 n2 PI-2

15. Issue • Fanout-reconverge • Duplicate PI-1 n1 n2 PI-2

16. Issue • Fanout-reconverge • Duplicate PI-1 Target PI-1 n1 n2 PI-2

17. XOR/XNOR Gate • Brute-force analysis • 3 structures for XOR • 3 structures for XNOR

18. Continuous XOR gates • How to record? • Super gate & DFS & Disjoint Set DFS Save as super gate Union & Save

19. Issue • Cont. AND vs. Cont. OR/NOR/NAND • If only 1 library appears – no problem • If both appear ? • AND or NOR? • Overlaps between XOR and cont. AND/… ? Target

20. Outline • Problem Formulation • Framework & Flow • Logical macro mapping • Continuous AND/NAND/OR/NOR/XOR/XNOR • Arithmetical macro mapping • Adder • Others • Framework • Cutting • Matching • Progress & Future Work

21. Adder 0 • Full adder • structural mapping

22. Adder 0 0 0 0 0

23. Framework • 1. Partition POs into PO macros Macro Macro Macro Macro PO macro 1 PO macro 2 PO macro 3

24. Framework • 2. For each PO’s TFIC (PO macro), determine the PIs with constraint K = 12, 11 ,10, … , 3 , 2, and produce sub-macros • E.g. K=12, which PIs will be selected? • Exhaustive (CNK < 64) /Random Sub-macro 1 Sub-macro 2

25. Framework • 2. For each PO macro, determine the PIs with constraint K = 12, 11 ,10, … , 3 , 2 • E.g. K=8 Sub-macro 3 Sub-macro 4

26. Framework • 3. For each sub-macro, after selecting the PIs, assign the constant values to create mini-macros • Random? • How many? 0, 1? 0, 1? Mini-macro 0, 1? 0, 1?

27. Framework • 3. For each mini-macro, after selecting the PIs, assign the constant values to create mini-macros • Rule (1-level) • Logic implication? • How many random? • Exhaustive (< 26=128) + random 1 0 mini-macro Random 0, 1 Random 0, 1

28. Framework • 4. Cut-and-Map • 5. Select the best mapping result in each PO macro • Greedy: cut-and-map from larger mini-macros to smaller mini-macros • Among the mini-macros with the same K constraint, select the best one and go to 6 if some mini-macros can be mapped • 6. Greedily select the mapping results among all PO macros Macro Macro Macro 20 8 35

29. Framework • 6. Greedily select the mapping results among all POs’ TFIC • Only consider disjoint PO macros Macro 1st 35 2nd 28

30. K cut • Leave number: 3 <= K <= 12 • Mode 1: return all cuts whose K <= 12 • Mode 2: ignore covered cuts • Max cut per node: 1000 • Result:

31. Matching • Lazy man’s semi-canonical form Input: TruthTable F Determine the polarity of F by the number of 1’s in TruthTable Determine the polarity of each variable by the number of 1s in the negative cofactor w.r.t. each variable Sort input variables by the number of 1s in their negative cofactors and permute inputs accordingly Output: canonicizedTruthTable F

32. Isolation between macros and other standard cells • Trick Macro Macro PPOs PPIs

33. More Issues • If there are overlaps between logic macro and arithmetical macro? • Select one of them… • More heuristics ?

34. design.v lib.v Verilog Parser blif AIG Resyn2 Optimize NMG+NAR Yes 1. node# decrease? Continuous AND OR map No Algorithm 3. 2. K cut Lazy man Adder Output Standard cell mapping Out.v

35. Outline • Problem Formulation • Framework & Flow • Logical macro mapping • Continuous AND/NAND/OR/NOR/XOR/XNOR • Arithmetical macro mapping • Adder • Others • Framework • Cutting • Matching • Progress & Future Work

36. Division of works & Progress • I/O • Wei-An • Logical macro mapping • Continuous AND/NAND/OR/NOR/XOR/XNOR • Yu-Min & W.-A • Arithmetical macro mapping • Adder • Others • Framework – C-.Y. & W.-A. • Cutting – Wei-An • Mapping – Ching-Yi & Wei-An 100% idea: 100% ; implementation: 90% idea: 100% ; implementation: 50% idea: 90% ; implementation: 0% 99% 30%

37. Future work • Implementation • Many issues • Continuous ANDs vs. others… • More heuristics …