1 / 9

ELEC1700 Computer Engineering 1 Week 10 Wednesday lecture Revision for Quiz 3 Semester 1, 2013

ELEC1700 Computer Engineering 1 Week 10 Wednesday lecture Revision for Quiz 3 Semester 1, 2013. Quiz 3. When? Scheduled lecture on Wednesday 22 May , 3:00–4:00pm = next week = week 11 Start time: 3:10pm Finish time: 3:50pm Where? MCTH lecture theatre What does it cover?

auryon
Download Presentation

ELEC1700 Computer Engineering 1 Week 10 Wednesday lecture Revision for Quiz 3 Semester 1, 2013

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ELEC1700Computer Engineering 1Week 10 Wednesday lectureRevision for Quiz 3 Semester 1, 2013

  2. Quiz 3 When? Scheduled lecture on Wednesday 22 May, 3:00–4:00pm = next week = week 11 Start time: 3:10pm Finish time: 3:50pm Where? MCTH lecture theatre What does it cover? material presented in weeks 7–9 What is it worth? counts for 10% of your final grade in ELEC1700

  3. Instructions to Candidates • Time allowed: Forty (40) minutes • One A4 page (double-sided) of student’s own notes is permitted • Answer ALL questions • Calculators are permitted • Total number of marks = 40 • Rough working may be done on the reverse side of each page

  4. Quiz format • 5 multiple choice questions (1 mark each)5 • 3 short answer questions (5 marks each) 15 • 2 longer questions (10 marks each)20 Total 40

  5. Q D EN Q • Sketch the Q output of the gated D latch whose D and EN inputs are shown below

  6. Sketch the Q output of a negative edge-triggered J-K flip-flop whose inputs are shown below CLK J K PRE/ CLR/ Q

  7. The circuit below has input A, and state Q1Q0. Sketch the state diagram for the circuit.

  8. Obtain the truth table for the circuit below, whose inputs are A, B, and C, and whose output is Z. The truth table of the 74138 3-to-8 decoder is on the next page

More Related