Asynchronous Circuit Compilation

1. Asynchronous Circuit Compilation Dr. Doug Edwards doug@cs.man.ac.uk

2. Overview: • Asynchronous circuits • Advantages • Asynchronous Design Paradigms • Syntax Directed Compilation • Handshake Circuits • Balsa • Datapath Compilation • Design Example - DMA Controller

3. Asynchronous (self-timed) Basics • Synchronous circuits • a global clock separates system states • A time domain view of system activity. • Asynchronous circuits • input changes separate system states • A sequence or trace domain view of system activity.

4. Why Asynchronous? • Low Power • data-driven: power is only used to do useful work • zero power when idle with instant restart • Low EMI • In a clocked circuit, all noise is correlated • Async circuits have “distributed” switching activity leading to uncorrelated EMI

5. Why Asynchronous? • No clock distribution problems • Composability/Modularity • facilitates IP reuse • Average Case Performance • exploit the fact that worst-case often occurs infrequently

6. Timing Models • Delay Insensitive (DI) • Delays in circuits & wires are arbitrary • Quasi-Delay Insensitive (QDI) • Similar to DI but assuming isochronic forks • Speed Independent (SI) • Wires have no delays, arbitrary gate delays • Bounded Delay • Single-sided timing constraints

7. Asynchronous Design Paradigms • AFSMs - for fast controllers etc • Traditionally hard • hazards, races ,state asigment problems • Research has led to new techniques • STG/Petri net based SI circuits • Burst-Mode circuits • Macromodule-like for larger systems • micropipeline approach, handshake circuits

8. Asynchronous Control • With no clock, some other means is required to co-ordinate control flow • Use a request/acknowledge handshake Req Ack Sender

9. Signalling Protocols • req & ack are abstractions: • layer a signalling protocol on top of them: • Two common protocols • 2-phase (transition signalling, NRZ) • 4-phase (Return-to-Zero signalling)

10. Data Validity Models • Self Timed • The validity of the data is encoded within the data itself – redundant coding • e.g. Dual Rail: each data bit requires two wires. 00 -> no data, 01 -> ‘0’, 10 -> ‘1’ • Bundled Data approach • conventional datapath • validity is assured by imposing timing constraints.

11. 2-phase Protocol • Events are transitions: º R eq 1 tr ansaction 1 tr ansaction Ac k v alid v alid

12. 4-phase protocol • Signals are returned to initial state after each transaction • Several possible interleavings of the signal transitions

13. Comparison of Approaches • 2-phase/4-phase • 2-phase conceptually simpler (once an event mind-set is adopted) • 2-phase circuits slower & more complex • think 2-phase, build 4-phase • Bundled-Data/Dual-rail • Current orthodoxy: bundled data is faster, lower power, smaller area with tolerancing task no worse than for a clocked design

14. Current Approach • QDI control • Bounded-Delay (bundled-data) datapath • 4-phase signalling Amulet3i

15. Asynchronous HDLs • Conventional programming languages lack 3 necessary constructs: • communication • parallelism/concurrency • sharing (of hardware) • Conventional HDLs lack adequate • fine-grain concurrency • channel based communication primitives

16. Asynchronous HDLs – 2 • Tangram , Balsa • CSP based + data types + … • based on underlying formal semantics • guarantees correct composition rules • easier composition than in sync circuits??? • transparent compilation • each production rule in the language translates to an intermediate handshake circuit • allows designer to infer circuit costs & performance from the program

17. Handshake Circuits - 1 • Circuits communicate along channels • Channels connect ports at circuit interface • Ports have: • Type • Direction • Sense

18. Handshake Circuits - 2 • Port type determines the number of data wires • no data wires == control only port! • Port direction is input, output or control only • Port sense • Active: initiates transfers • Passive: responds to requests

19. Micropipeline-Style Circuits: Push Circuits: Circuit waits for data req req data data cct ack ack passive input active output

20. Micropipeline-Style Circuits: Push Circuits: data arrives req req data data cct ack ack

21. Micropipeline-Style Circuits: Push Circuits: data validity signalled req req data data cct ack ack

22. Micropipeline-Style Circuits: Push Circuits: circuit accepts data req req data data cct ack ack

23. Micropipeline-Style Circuits: Push Circuits: circuit signals data taken req req data data cct ack ack

24. Micropipeline-Style Circuits: Push Circuits: Circuit outputs data req req data data cct ack ack

25. Micropipeline-Style Circuits: Push Circuits: Circuit signals validity req req data data cct ack ack

26. Micropipeline-Style Circuits: Push Circuits: receiver takes data req req data data cct ack ack

27. Micropipeline-Style Circuits: • 4-phase protocol not detailed • Previous circuit decoupled input and ouput • implies a latch inside the handshake circuit • An alternative is for the input handshake to enclose the output handshake

28. Enclosed Handshake: Push Circuits: data arrives req req data data cct ack ack

29. Enclosed Handshake: Push Circuits: data validity signalled req req data data cct ack ack

30. Enclosed Handshake: Push Circuits: circuit accepts data req req data data cct ack ack

31. Enclosed Handshake: Push Circuits: Circuit outputs data req req data data cct ack ack

32. Enclosed Handshake: Push Circuits: Circuit signals validity req req data data cct ack ack

33. Enclosed Handshake: Push Circuits: receiver takes data req req data data cct ack ack

34. Enclosed Handshake: Push Circuits: input handshake completes No latch required req req data data cct ack ack

35. Tangram Style Circuits Pull Circuits: active ported circuits/ control driven req req data data cct ack ack active input port

36. Tangram Style Circuits Pull Circuits: Circuit demands data req req data data cct ack ack

37. Tangram Style Circuits Pull Circuits: data is sent on demand req req data data cct ack ack

38. Tangram Style Circuits Pull Circuits: data is accepted and can then be released req req data data cct ack ack

39. Balsa • Language for synthesising large async circuits & systems • CSP/OCCAM background • Tangram-like • based on Tangram compilation function • compiles to a small (but expanding) set of handshake circuits • origins: ESPRIT EXACT project

40. Balsa Language Features • Data types based on sequence of bits • Arrays and records are bit-based • Element extraction is by array slicing • Strict data typing • Structural iteration • Arrayed channels • Parameterised & recursive functions

41. Balsa Language Features • Enclosed selection semantics • Allows passive ported circuits • Allows push (micropipeline-style) circuits • Allows unbuffered (latch-free) circuits • Can be considered a restricted form of Burns’ probe construct.

42. Balsa Source

43. Example: Single Place Buffer import [balsa.types.basic] public type word is 16 bits procedure buffer (input i : word; output o : word) is local variable x : word begin loop i -> x; -- Input communication o <- x -- Output communication end end library mechanism visibility type declaration channel declarations procedure definition implies latch repeat forever sequential operation read input channel into local variable x output local variable x to output channel

44. Buffer Handshake Circuit Single-place buffer repeater  activation channel # sequencer ; transferrer i o x T T variable

45. Buffer Handshake Circuit Single-place buffer repeater is activated  # ; i o x T T

46. Buffer Handshake Circuit Single-place buffer Sequencer handshakes to left transferrer  # ; i o x T T

47. Buffer Handshake Circuit Single-place buffer transferrer requests data from environment  # ; i o x T T

48. Buffer Handshake Circuit Single-place buffer data transferred to variable x  # ; i o x T T

49. Buffer Handshake Circuit Single-place buffer variablehandshake completes  # ; i o x T T

50. Buffer Handshake Circuit Single-place buffer transferrerhandshake completes to environment  # ; i o x T T