WP3 Microelectronics and interconnection technology

1. WP3 Microelectronics and interconnection technology Hans-Günther Moser - MPI Valerio Re - INFN AIDA kick-off meeting, February 18, 2011

2. WP3 participants Task 2 (3D interconnection): • Participants: AGH-UST, CERN, CEA, CNRS (CPPM and IPHC), CSIC-CNM, UB, INFN, MPG-MPP, UBONN, STFC, UU • Associates: IPASCR, NTUA, UNIGLA, UNILIV, FOM Task 3 (Shareable IP blocksfor HEP): • Participants: AGH-UST, CEA, CERN, CNRS (LAL and LPNHE) • Associates: INFN-MI, INFN-PV andUBONN

5. Aim of the WP3 kick-off meeting The aim of this first meeting was to define a coherent program, and to start a selection process among the many options that are available for both 3D integration and IP blocks, obviously taking into account manpower and funding limitations. Some decisions have to be taken in a relatively early stage of the project (e.g., how to procure CMOS chips for 3D integration), others require to establish contacts with industry (for 3D interconnection steps), which is an important part of WP3. 5

6. WP3.2:3D interconnection The aim is to build a demonstrator of a 3D vertically integrated pixel sensor, which provides a tool to qualify the technologies that are involved in 3D integration and makes them accessible to the community. WP3 plans to follow a “via last ” approach to 3D integration to build a 2-layer device in heterogeneous technologies, where the two layers are fabricated independently, and TSVs (Through Silicon Vias) and interconnections are made as the last steps of the process. 6

7. The WP3 3D demonstrator: combining a set of diverse technologiestobuild a 4-side buttabledevice Choice of CMOS technology (0.13, 0.25, 0.35 mm) and foundry, design of a readout chip Choice of interconnection technology (mechanical and electrical bonding) Choice of technology for TSV (Through-Silicon-Via) Choice of sensor (CMOS sensors, high resistivity planar or “3D” pixels) Except probably for sensors, WP3 will likely pursue one option for each item, making a choice based on scientific interest, accessibility and available resources 7

8. Sensors Possible Manufacturers/Institutes: CNM, FBK, MPP, VTT(made presentations at parallel session), Micron, Sintef, CMOS foundries Possible selection criteria: wafers size sensor thickness (thin) edgeless copper/tin layer (for eutectic bonding) Compatibility with advanced bonding technologies 8

9. Sensors at WP3 parallelsession:fullydepleted, high resistivitypixels FBK (Trento, Italy) Planar pixels, full-”3D” pixels with slim edge; active edge sensors also being developed VTT (Finland) Edgeless detectors, R&D towards 4-side buttable devices (TSVs, flip-chip bonding) MPI-HLL (Munich) Thinpixelsensorswith UBM (copper on Ti/W) IMB-CNM (Barcelona) Activeedge, “3D“ pixels, bumpbonding (UBM andbumpgrowing) 9

10. CMOS readoutcircuitsfor 3D integration • Possible Manufacturers: • IBM (via CERN),IBM (via MOSIS), Chartered (via Equipic), Tezzaron/Chartered 3D (via CMP/CMC/MOSIS), UMC, AMS (via EUROPRACTICE), others • Possible selection criteria: • CMOS technology node (350nm, 250nm, 130nm, 90nm…) • Full wafer access (postprocessing for 3D interconnection) • Yield • Cost • Accordingtoourmilestones, wehavetofreeze the CMOS ASIC design bymid 2012. Thisisnecessaryto complete the program on 3D integrationwith a full qualificationof the demonstrator and of the relevanttechnologies. 10

11. An approach to 3D CMOS ASICs:the 3D-IC consortium • Presentation by G. Traversi (Univ. Bergamo): 3D integrated circuits with the Tezzaron/Global Foundries process • This approach is followed by the 3D-IC consortium promoted by Fermilab and including several WP3 partners. • It is a “via first” process, where TSVs are drilled at the foundry in the early stages of CMOS wafers processing. • Very high density interconnections (< 10 mm) are possible with this technique. 2-layer CMOS chips for pixel readout with many pixel-level interconnections 11

12. CMOS ASICs: the AIDA-WP3 approach • As an AIDA goal, we chose the option of qualifying a "via last" process (TSVs drilled outside the CMOS foundry, on fully processed CMOS wafers). • This could meet the requirements of applications where need for the high-density TSVs of Tezzaron is not so stringent. • In most of our applications, we might need TSVs only in peripheral regions corresponding to the bonding pad area. In this case, TSV pitch (several tens of mm) and number (several hundreds) are relatively low. 12

13. How WP3 mayget CMOS ASICs • This is a key issue, and was the focus of most of the discussion in the parallel session. • Considering funding limitations, two strategies are possible: • Choose CMOS 130 nm (most pixel readout designs are presently done in this node) and share the costs of an engineering run (necessary to get full wafers) with other partners and/or projects. This could be organized by CERN. • Choose a less scaled technology, such as 350 nm. • It would be nice to build a dedicated chip that is optimized for 3D integration; most likely, this should be an adaptation of an existing chip (restricting the choices of 130 nm foundries). 13

14. Post processing and 3D interconnection Possible manufacturers: IZM Berlin, EMFT (ex IZM Munich), IMEC, LETI, VTT, T-Micro, Tezzaron, Ziptronix, others (with a large diversity of approaches) Possible Selection Criteria: post processing possibilities (via last) thinning via density Accessibility Cost 14

15. 3D postprocessing at the WP3 parallelsession MPI-HLL (Munich) Macchiolo: SLID interconnectiontechnologyand TSVs fortheupgradeofthe ATLAS pixelsystem Fraunhofer EMFT process: 15

16. WP3 interactionwithindustryfor 3D integration • Weagreedto concentrate on onesupplierfor the 3D processing, whichisquiteexpensive. • WP3 willorganizea 1-day workshop withindustries and researchinstituteswhichmayprovide 3D technologytoour network. • Thiswillbeanopportunitytodiscusswiththem and understandhowthey can meetourneeds. • Thiswillbe the first steptowards the choiceof the 3D technologywewilluseforourdemonstrator. 16

17. WP3-3 task (I) Shareable IP blocks for HEP • Goal : provide 2 lots of IP blocks for the HEP needs with full documentation and laboratory tests • Lead institutions : CERN + LAL • Choose the best techno at best price (MPW center) • Gather the different designs • Send them to MPW center • Provide efficient interface between designers and MPW center • Centralize the documentation of blocks and test results • Organize users meeting • Other participant labs : AGHT-UST, IRFU, LPNHE • Associated labs : INFN-Mi, INFN-Pv, U Bonn, others ? Gisèle Martin-Chassard - AIDA Kick off meeting

18. WP3-3 task (II) • 1srt set of IP blocks (November 2012): • managed by CERN • Technology : DSM CMOS (mostly 130nm, 65nm could be supported also); presentation by MarekIdzik (AGH-UST) on IBM 130nm blocks • electronics for trackers • Radiation hardness • 2nd set of IP blocks (September 2014): • Managed by LAL • Technology : SiGe 130nm, 180nm or 350 nm ? (IBM, AMS …) • MPW center : depend on techno (CMP, MOSIS …) • Electronics for calorimeters and TPCs : high dynamic range, need of precise capacitors and resistors, … • Blocks (for both sets): low noise and fast amplifiers, fast ADCs, TDC (100ps), Bandgap, Rad-tol memory, PLL, SEU resistant flipflop, high speed LVDS, DC-DC … Gisèle Martin-Chassard - AIDA Kick off meeting

19. Conclusions • In this WP3 meeting, wemade the first stepstowards the technologychoicesthat are neededtobuildour 3D demonstrator and to design IP blocks. • The 3D integrationofdevices in heterogeneoustechnologymay open up varioussolutions(e.g. CMOSreadout + high res. sensor, analogCMOS + digitalCMOS, CMOSsensor + digitalCMOS). • Wemovedforwardto create aneffective network thatwillprovide the community with know-how and accessto 3D integrationtechnologiesforadvanced pixel sensors, and to IP blocksforreadoutintegratedcircuits in a varietyofdetectors and applications. 19

20. Backup slides

21. WP3 Tasks Task 1. Coordination and Communication • To coordinate and schedule the execution of the WP tasks • To monitor the work progress and inform the project management and the participants within the WP • To follow-up the WP resource utilization • To prepare the internal and Deliverable Reports Task 2. 3D Interconnection • Creation and coordination of a framework to make 3D interconnection technology available for HEP detectors • Organisation of dedicated fabrication of sensors and electronics optimized for 3D interconnection • Construction of demonstrator detectors using 3D technology to access this technology Task 3. Shareable IP Blocks for HEP • Creation and coordination of a framework for the design of low and medium complexity microelectronics libraries and blocks in advanced submicron technologies to be made available to the community of users in HEP • Organization of the design and qualification of a set of blocks using selected and qualified technologies • Distribution and documentation of the library of functional blocks • Organisation of regular Microelectronics Users Group meetings to exchange information, plan and coordinate actions related to the creation of a shared library of macro blocks.