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Flip-Flops

Flip-Flops. Module M10.2 Section 7.1. D CLK Q !Q. 0 1 0 1 1 1 1 0 X 0 Q 0 !Q 0. D Latch. S. !S. D. Q. CLK. !Q. !R. R. Note that Q follows D when the clock in high, and is latched when the clock goes to zero. D. Pulse-narrowing circuit. CLK.

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Flip-Flops

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  1. Flip-Flops Module M10.2 Section 7.1

  2. D CLK Q !Q 0 1 0 1 1 1 1 0 X 0 Q0 !Q0 D Latch S !S D Q CLK !Q !R R Note that Q follows D when the clock in high, and is latched when the clock goes to zero.

  3. D Pulse-narrowing circuit CLK D NCK Q !Q D CLK Q !Q 0 1 0 1 1 1 1 0 X 0 Q0 !Q0 0 0 1 1 1 0 X 0 Q0 !Q0 D Flip-Flop S !S Q NCK !Q !R R

  4. Pulse-Narrowing Circuit

  5. D Q CLK !Q D CLK Q !Q 0 0 1 1 1 0 X 0 Q0 !Q0 D Flip-Flop Positive edge triggered D gets latched to Q on the rising edge of the clock.

  6. D Q CLK !Q D Flip-Flop pulse width CLK setup time hold time y z propagation delay

  7. Making a positive edge-triggered D Flip-Flop from Master-Slave D Latches x y z input output D Q D Q master slave CLK’ E E CLK CLK CLK’ x y z

  8. D Q CLK !Q D CLK Q !Q 0 0 1 1 1 0 X 0 Q0 !Q0 D Flip-Flop Positive edge triggered D gets latched to Q on the rising edge of the clock.

  9. OE CLK D Q Pin CLK !Q Polarity X Feedback CLK GAL 16V8 D Flip-Flops

  10. Q0.D D Q Q0 CLK !Q !Q0 Q0.D = !Q0 Divide-by-2 Counter CLK Q0 Q0.D = !Q0

  11. Q0.D D Q Q0 CLK !Q !Q0 Q0.D = !Q0 div2cnt.abl MODULE Div2Cnt TITLE 'Divide By 2 Counter, A. Student, 7/20/02' DECLARATIONS " INPUT PINS " PB PIN 10; " push-button switch (clock) " OUTPUT PINS " Q0 PIN 35 ISTYPE 'reg buffer'; " LED 8 [A,B,C,D,E,F,G,DP] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com'; Segments = [A,B,C,D,E,F,G]; " 7-segment LED display Registered Buffer output

  12. Q0.D D Q Q0 CLK !Q !Q0 Q0.D = !Q0 div2cnt.abl (cont’d) EQUATIONS Q0.c = PB; Q0.d = !Q0; DP = PB; " decimal point @radix 16; truth_table ( Q0 -> Segments ) " 7-segment display 0 -> 7E; 1 -> 30; END Div2Cnt Counts 0, 1, 0, 1 …

  13. Registered Feedback in GAL16V8

  14. OE CLK D Q Pin CLK !Q Polarity X Feedback CLK GAL 16V8 D Flip-Flops On RESET Q is cleared to 0. Therefore, output pin is HIGH

  15. Simulation File, div2cnt.si CUPL Simulation File

  16. Simulation File, div2cnt.si CUPL Simulation File Note: Power-on reset sets all outputs high. Therefore, first test vector MUST go LOW.

  17. CUPL Simulation Output

  18. A 1-Bit Register

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