1 / 19

Flip Flops

Flip Flops. Unit-4. Flip Flop. A basic sequential circuit is a flip-flop Flip-flop has two stable states of complementary output values. SR Flip Flop. SR Flip Flop. SR (set-reset) flip-flop based on two nand gates. Clocked SR Flip Flop Circuit.

carmour
Download Presentation

Flip Flops

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Flip Flops Unit-4

  2. Flip Flop A basic sequential circuit is a flip-flop Flip-flop has two stable states of complementary output values

  3. SR Flip Flop

  4. SR Flip Flop SR (set-reset) flip-flop based on two nand gates

  5. Clocked SR Flip Flop Circuit Clock controlled flip-flop changes its state only when the clock C is high

  6. Clocked SR Flip Flop Circuit with Reset Some flip-flops have asynchronous preset Pr and clear Cl signals. Output changes once these signals change, however the input signals must wait for a change in clock to change the output

  7. Edge Triggered Flip Flop Edge triggered flip-flop changes only when the clock C changes

  8. Positive Edge Triggered Flip Flop Positive-edge triggered flip-flop changes only on the rising edge of the clock C

  9. Negative Edge Triggered JK Flip Flop

  10. T D J J Q Q f f f f Q Q K K T Q D Q Q Q f f (D-latch) Delay Flip-Flop Toggle Flip-Flop Other Flip Flops

  11. t loop t f D Q t 1 Q f Signal can race around during = 1 f Race Problem

  12. SLAVE MASTER SI J S Q S Q Q RI K Q R R Q Q f PRESET J Q f Q K CLEAR Master-Slave Flip Flop Implementation Master transmits the signal to the output during the high clock phase and slave is waiting for the clock to change this prevents race conditions

  13. Shift Registers

  14. Shift Registers

  15. RIPPLE Counter

  16. UP- COUNTER

  17. MOD-3 Counter

  18. RING Counter

  19. JHONSON Counter

More Related