STT-RAM Feasibility Study

1. STT-RAM Feasibility Study Amr Amin UCLA Jan 2010

2. Outline • Introduction • Memory Cell • Cell Area Calculation • Write Current Limitations • Reading Techniques and Limitations • Effect of Process Variations and Mismatch • MTJ Feasible Region • Area Minimization

3. Introduction • The need for a universal memory • Brief history of magnetic device memories • Description of the MTJ device • Literature survey • … • … • Summary of the paper flow

4. STT-RAM Cell • Schematic diagram • Anti-parallelizing / Parallelizing currents • Read disturb problem • Cell layout • Basic cell area vs. access device width

5. Effective Cell Area • This takes into account the overhead of: • Column MUX • Row decoder • Sense Amp • I/O circuits • Area optimization should also consider: • Optimum memory partitioning • Access transistor vs. column MUX areas

6. Write Current Limitations • MOS drain current equation and fitting • Maximum allowed RP and RAP for certain write current(s) • Column MUX design (justification for using T-gates instead of P-transistors) • Effect of each of the four MUX devices on the maximum allowed resistances

7. NMOS Drain Current

8. PMOS Drain Current

9. Maximum RAP

10. Maximum RP

11. Constant ‘Read’ Signal Contours • Voltage Sensing • Current Sensing

12. Process Variations • MOS variations: • Min K and max VT • Reduce the maximum allowed RP and RAP • Decrease the ‘read’ signal (decreasing IR or VR) • Mismatch: • Degrades sensitivity of the SA • Higher nominal read signal is required • MTJ variations: • MgO thickness and area variations • Distort the nominal feasible region of the MTJ

13. Process Variations

14. MTJ Feasible Region • What is the MTJ feasible region in the RP­RAP plan given the following: • Desired write current • Desired basic cell area • Column MUX width • Certain technology • Certain variations (Yield) • Matching parameters (Yield)

15. Typical MOS Variations MOS & MTJ Variations Dec-2009 Tape-out • IBM-90nm-CMOS • VWL = VDD = 1 V • IWR = 500 μA • Wa=2.56 μm • WP,MUX=16 μm • WN,MUX=8 μm • MOS K varies +/- 20% • MOS VT varies +/- 50mV • MTJ: RA = 2 Ω.μm2 • MTJ: KRA = 34 Ω.μm2/nm • MTJ: TMR = 100% • MTJ: KTMR = 200 %/nm • MTJ: ΔtMgO = 0.2 Ao • Current Sensing: VR= 600 mV • Current Sensing: ΔIR= 20 μA

16. SRAM-Area Constraint

17. Flash-Area Constraint

18. DRAM-Area Constraint

19. Area Minimization Problem • Minimize: Effective cell area • Subject to: • MTJ resistances and write current value • MTJ variations • Parallelizing/Anti-parallelizing Write current equations • MOS variations and matching parameters • Speed must come into picture to constrain the optimum memory partitioning • May be able to formulate this into a standard optimization problem form that can be solved efficiently

20. Remaining Issues • Analyzing Read/Write Speed and adding this as a constraint in the optimization problem • The same with power • More analysis is needed for the minimum required sensing signal (current or voltage) • CMOS mismatches and offset • Signal degradation due to MgO thickness variation • Possible signal degradation due to CMOS process variation (dependant on the SA implementation) • Regenerating all results for different technologies