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STT-RAM Circuit Design

STT-RAM Circuit Design. Column Circuitry Simulation (IBM 65nm) Fengbo. Design Constraints. MTJ Char. (From Jianping’s group) R P ≈ 744 Ω TMR ≈ 136% Max writing current 1.5 mA for P->AP 630 uA for AP->P Min writing current Reading

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STT-RAM Circuit Design

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  1. STT-RAM Circuit Design Column Circuitry Simulation (IBM 65nm) Fengbo

  2. Design Constraints • MTJ Char. (From Jianping’s group) • RP ≈ 744Ω • TMR ≈ 136% • Max writing current • 1.5 mA for P->AP • 630 uA for AP->P • Min writing current • Reading • [220 uA,1 ns] current has 1% probability of disturbance. • Short pulse read (<300 ps) is needed (Breakdown voltage = 1.1V)

  3. MTJ Sub-array • 64x512, 32 kb sub-array • 64 WL • 4 128-bit words on each WL • 4 columns share 1 sense amp& write driver through 4-1 mux • 40F2 cell size used.

  4. Column Circuitry

  5. Write • P->AP • Vgs_P= VWL - Vdrop ≈ VDDW • Vds_P = VDDW – Vdrop – Vmtj_P • AP->P • Vgs_AP = VWL – Vdrop – Vmtj_AP • Vds_AP= VDDW - Vdrop – Vmtj_AP • Boosting VWL • Limited by Vgs_P (0.1 V margin) • Boosting VDDW • Limited by Vds_AP (0.5-0.6 V margin) • Have to use thicker oxide devices in the write driver circuit (in red)

  6. Write Current Comparison • Compare 3 cases of boosting voltage • Constraints • VDDW < VDDmax • Vgs, Vds < VDDmax • For all devices

  7. Write Current Comparison Result • Boost up VDDW to 1.1V, VWL to max - 21-22% gain • Boost up VDDW to 1.5V, VWL to max - 30-33% gain • Medium oxide device used, 2.2x bigger write driver • Boost up VDDW to 1.9V, VWL to max - 35-37% gain • Thick oxide device used, 7.6x bigger write driver

  8. Read • Short pulse reading

  9. Read simulation result • 270 ps only read current pulse • 150 ps pulse of control signal • 270 ps pulse current through MTJ • Read time:157 ps for Rp,167 ps for Rap

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