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VHDL Description

VHDL Description. 1. Behavioral Description ( 동작묘사 ) - Functional or Algorithm Description - High Level Language Program 과 유사 - 문서화를 위해서 우수 - VHDL 의 순 차문 (Process) 사용 2. Dataflow Description ( 데이터 흐름 묘사 ) - Behavioral Description 보다 한 단계 낮은 Level

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VHDL Description

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  1. VHDL Description 1. Behavioral Description (동작묘사) - Functional or Algorithm Description - High Level Language Program 과 유사 - 문서화를 위해서 우수 - VHDL의 순 차문 (Process) 사용 2. Dataflow Description (데이터 흐름 묘사) - Behavioral Description보다 한 단계 낮은 Level - Boolean Function, RTL, 또는 연산자 (AND, OR) 표현 3. Structural Description (구조묘사) - 가장 하드웨어적 표현에 가까움 - 구성요소 (component) 및 연결(port) 까지 표현- 합성을 위해 사용 4. Mixed Description (복합묘사) - 지금까지 기술된 방식을 혼합적으로 사용 - Simulation 및 합성 가능

  2. 1. VHDL Description 1. two 입력 AND gate Library ieee; Use ieee.std_logic_1164.all; Entity and_2 is port( a, b : in std_logic; y : out std_logic ); end and_2; Architecture dataflow of and_2 is beginy <= a and b; end dataflow;

  3. 1. VHDL Description 2. two-입력 OR gate Library ieee; Use ieee.std_logic_1164.all; Entity or_2 is port( a, b : in std_logic; y : out std_logic ); end or_2; Architecture dataflow of or_2 is beginy <= a or b; end dataflow;

  4. 1. VHDL Description 3-1 AND-OR-Signal Y=(a and b) or C 3-2. OR-AND-Signal Y=(a or b) and C

  5. 1. VHDL Description AND-OR-Signal, OR-AND-Signal 의 data flow 표현 Library ieee; Use ieee.std_logic_1164.all; Entity ANDORS is port ( A, B, C : in std_logic; Y : out std_logic ); End ANDORS; Architecture dataflow of ANDORS is signal aandb : std_logic; Begin aandb <= A and B; Y <= a and b or C End dataflow; Library ieee; Use ieee.std_logic_1164.all; Entity ORANDS is port ( A, B, C : in std_logic; Y : out std_logic ); End ORANDS; Architecture dataflow of ORANDS is signal aorb : std_logic; Begin aorb <= A or B; Y <= a or b and C End dataflow;

  6. a y b 1. VHDL Description 4. 4-bits OR gate library ieee; use ieee.std_logic_1164.all; entity or_4bits is port( a, b : in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0) ); end or_4bits; architecture dataflow of or_4bits is begin y <= a or b; end dataflow;

  7. 1. VHDL Description 5. 2x1 Mux 의 behavioral description library ieee; use ieee.std_logic_1164.all; entity mux21 is port( a,b : in std_logic; s : in std_logic; x : out std_logic); end mux21; Architecture select_1 OF mux21 IS BEGIN mu: PROCESS (a, b, s) BEGIN IF s = '0' THEN x <= a; ELSE x <= b; END IF; END PROCESS mu; END select_1 a MUX x b S x <= a when (s='0') else b;

  8. 1. VHDL Description • 5-1. 2x1 Mux 의 behavioral description ; Case 문을 이용한 표현 • case s is • when '0' => x<= a; • when others => x<= b; • end case; • 5-2. 2x1 Mux 의 behavioral description ; With Select 문을 이용한 표현 • WITH s SELECT • x <= a WHEN ‘0’, • b WHEN others;

  9. x S :sum C : carry y half adder 1. VHDL Description 6. Half-adder • S=xy′+x′y • C=xy

  10. 1. VHDL Description 6-1. Half-adder dataflow description library ieee; Use ieee.std_logic_1164.all; Entity half_add is port( a,b : in std_logic; s,c : out std_logic); end half_add; Architecture RTL_1 of half_add is begin S <= A xor B; C <= A and B; end RTL_1;

  11. 1. VHDL Description 6-2. Half-adder behavior description architecture Beh of half_add is begin process begin if (a = b) then S <= ‘0’ ; else S <= ‘1’ ; end if ; if (a = ‘1') and (b = ‘1’) then C <= ‘1’ ; else C <= ‘0’ ; end if ; end process ; end Beh ;

  12. cin cout 1. VHDL Description 7. Full Adder x Sum y full adder Cout Cin • Sum=x’yz+x’yz+xy’z’+xyz • Cout=xy+xz+yz=xy+xy’z+z’yz

  13. 1. VHDL Description Signal 지정필요 7. Full Adder t1 sum t2 Half Adder t3 cout cin

  14. 1. VHDL Description 7-1. Full Adder dataflow description library ieee; use ieee.std_logic_1164.all; entity full_add is port( x, y, Cin : in std_logic; sum, Cout : out std_logic); end full_add; architecture fadd of full_add is signal t1, t2, t3 : std_logic; begin t1 <= a xor b; t2 <= a and b; t3 <= t1 and cin; sum <= t1 xor cin; cout <= t2 or t3; end fadd;

  15. 1. VHDL Description 7-2. Full Adder Behavior description architecture beh of full_add is begin process variable I : integer ; begin I := 0; if (x = ‘1’) then I := I + 1 ; end if; if (y = ‘1’) then I := I + 1 ; end if; if (Cin = ‘1’) then I := I + 1 ; end if; if (I = 1) or (I = 3) then Sum <= ‘1’ ; else Sum <= ‘0’; end if; if (I > 1) then Cout <= ‘1’ ; else Cout <= ‘0’; end if; wait on x, y, Cin ; end process ; end beh ; x,y,cin이 되는 개수를 센다

  16. 1. VHDL Description 7-3. Full Adder Structural description library ieee; use ieee.std_logic_1164.all; use ieee.std_unsigned.all; use ieee.std_logic_arith.all; entity full_add is port( x, y, Cin : in std_logic; sum, Cout : out std_logic); end full_add; architecture fadds of full_add is signal t1, t2, t3 : std_logic; Component OR_3 port (I1, I2 : in std_logic; O : out std_logic End Component Component half_add port (A, B : in std_logic; S, C: out std_logic); End Component Begin HA1:Half_add port map(X,Y,t1,t2); HA2:Half_add port map(t1,Cin,sum,t3); ORG: OR_3 port map(t2,t3,Cout) end fadds;

  17. 1. VHDL Description 8. Comparator Y= (A XOR B)’ : A와B 가 같으면 1을 출력, 틀리면 0을 출력 library ieee; use ieee.std_logic_1164.all; entity comp is port( A, B, Cin : in std_logic; Y : out std_logic); end comp; architecture compdata of comp is begin Y <= not(a xor b); end compdata;

  18. 1. VHDL Description 9. 3x8 Decoder 3비트 입력을 받아 비트변화에 따라서 8개의 출력 중 하나를 1로 내보내는 회로

  19. 1. VHDL Description 9. 3x8 Decoder Behavioral description LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY decoder3_8 IS PORT( xyz : IN STD_LOGIC_VECTOR (2 downto 0); D : OUT STD_LOGIC_VECTOR (7 downto 0)); END decoder3_8 ; ARCHITECTURE Beha OF decoder3_8 IS BEGIN WITH xyz SELECT y<="00000001" WHEN "000", "00000010" WHEN "001", "00000100" WHEN "010", "00001000" WHEN "011", "00010000" WHEN "100", "00100000" WHEN "101", "01000000" WHEN "110", "10000000" WHEN "111", "00000000" WHEN others; END beha;

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