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ASYNCHRONOUS CIRCUITS

Learn about the distinctions between synchronous and asynchronous sequential circuits, timing constraints, analysis processes, and the significance of studying asynchronous circuits for digital logic design. Explore state diagrams, synthesis steps, and more.

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ASYNCHRONOUS CIRCUITS

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  1. ASYNCHRONOUS CIRCUITS

  2. A general model of a sequential circuit DSD

  3. Asynchronous sequential • Synchronous sequential DSD

  4. What is the difference between Synchronous and asynchronous sequential circuits ??? • Synchronous Sequential: • States are represented by F/Fs. • Logic is controlled by clock pulse => ‘pulse mode’. • Asynchronous Sequential: • No F/F. • No clock: change of state is triggered by level (0/1) of inputs (includes present state + FB from o/p). • Operates in ‘fundamental mode’:“ Change in i/p should be such that there is sufficient time to allow circuit to reach a ‘stable state’ ”. DSD

  5. Synchronous sequential circuits • The state variables are represented by flip-flops that are controlled by a clock. • The clock is a periodic signal that consists of pulses. • Changes in state can occur on the positive or negative edge of each clock pulse. • Since they are controlled by pulses, synchronous sequential circuits are said to operate in pulse mode. DSD

  6. Asynchronous sequential circuits • Sequential circuits that do not operate in pulse mode and do not use flip-flops to represent state variables. • Changes in state are not triggered by clock pulses. • Changes in state are dependent on whether each of the inputs to the circuit has the logic level 0 or 1 at any given time. DSD

  7. Asynchronous sequential circuits • To achieve reliable operation, the inputs to the circuit must change in a specific manner. • There must be sufficient time between the changes in input signals to allow the circuit to reach a stable state, which is achieved when all internal signals stop changing. • A circuit that adheres to these constraints is said to operate in the fundamental mode. DSD

  8. Why to study Asynchronous circuits? • To study the timing issues caused by propagation delays in logic circuits (these are avoided in ‘synch circuits by using clock as a synchronizing mechanism). • ACTUALLY, all practical circuits are ASYNCHRONOUS !! • We will study some design approaches suitable for small circuits & try understand timing constraints problems….. DSD

  9. Asynchronous circuits: basic requirements • No clock for synchronizing. • Inputsdo NOTchange SIMULTANEOUSLY DSD

  10. ASYNCHRONOUS BEHAVIOR DSD

  11. Example: SET-RESET Latch DSD Circuit with modeled gate delay

  12. Example: SET-RESET Latch • : Combined propagation delay through the two NOR gates. • The NOR gates shown are ideal. • y = Q - Present state variable. • Y - Next state variable. • After the Δ time delay, y takes the value of Y . DSD

  13. ANALYSIS DSD

  14. The Analysis Process - Steps involved • Each FB path is cut (only one cut per loop) & a delay element inserted at that point: • I/P to each delay element = NS variable ‘Y’. • O/P of each delay element = PS variable ‘y’. • Minimal no. of cuts to be made - called ‘cut set’. • Derive expressions for NS & O/P from the circuit. DSD

  15. The Analysis Process - Steps involved • Derive excitation table corresponding to NS & O/P expressions. • Obtain ‘flow table’ (associate arbitrary names like S1, S2… )with encoded states. • Derive state diagram from the flow table. DSD

  16. State assigned table By analyzing the SR latch, we can derive a state-assigned table: DSD

  17. Analysis: How the circuit behaves. • When y = Y , the state of the circuit will not change. We say that the circuit is stable under such conditions. • When ever an input causes the condition y /= Y , the circuit is not stable. • After the time delay, the circuit changes to the new present state. DSD

  18. Analysis: How the circuit behaves. Discuss in details for each combination of SR when y = 0 and y = 1 how state changes – Refer “Fundamentals of digital logic with VHDL design” byStephen Brown. DSD

  19. FSM model for the SR latch DSD

  20. State table • The concept of stable states is very important in the context of asynchronous sequential circuits. • For a given valuation of inputs, if a circuit reaches a particular state and remains in this state, then the state is said to be stable. • To clearly indicate the conditions under which the circuit is stable, it is customary to encircle the stable states in the table DSD

  21. State table • From the state-assigned table, we can derive state table. • The state names A and B represent the present states y = 0 and y = 1, respectively. DSD

  22. State diagram • Since the output Q depends only on the present state, the circuit is a Moore-type FSM. • The state diagram represents the behavior of this FSM. DSD

  23. SYNTHESIS DSD

  24. Synthesis – Steps involved • Draw a state diagramfor the FSM that realizes the required functional behavior. • Derive flow table. Reduce no. of states (if possible). • Perform state assignment & derive excitation table. • Obtain NS & O/P expressions. • Construct the circuitthat implements these expressions. DSD

  25. Synthesis: Opposite task of analysis • Given the state table, we can synthesize an asynchronous circuit. DSD

  26. Synthesis • After performing the state assignment, we have the state-assigned table. • This table represents a truth table for Y , with the inputs y, S, and R. DSD

  27. Synthesis • Deriving a minimal product-of-sums expression yields: • Using NOR gates we can realize it as: DSD

  28. ANALYSIS OF MEALY MODEL DSD

  29. Mealy representation of the SR latch • The outputs produced when the circuit is in a stable state are the same as in the Moore model, namely 0 in state A and 1 in state B. • In the Mealy model, the output is supposed to be affected immediately by a change in the input signals. DSD

  30. Mealy representation of the SR latch: State table. DSD

  31. Mealy representation of the SR latch: State diagram. DSD

  32. Mealy representation of the SR latch. • The entry is kept un specified when there is a change of state because we cannot gain anything more if the output value is changed a little sooner. • Anyway the out put will change the value when it achieves the next state. • Leaving the entry unspecified allows us to assign either 0 or 1 to it, which may make the circuit that implements the state table somewhat simpler. DSD

  33. TERMINOLOGY DSD

  34. Terminology in asynchronous sequential circuit design • Instead of a “state table,” it is more common to speak of a flow table, which indicates how the changes in state flow as a result of the changes in the input signals. • Instead of a “state-assigned table,” it is usual to refer to a transition table or an excitation table. • A flow table will define the state changes and outputs that must be generated. An excitation table will depict the transitions in terms of the state variables. DSD

  35. Thank You DSD

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