MEMS Class 4 Fabrication Processes for MEMS Mohammad Kilani

1. MEMS Class 4 Fabrication Processes for MEMS Mohammad Kilani

2. Basic Microfabrication Processes

3. Basic Processes in Micromachining • Deposition • Oxidation • Physical Deposition: (deposition takes place without the need for chemical reaction) spin coating, evaporation, sputtering, ion implantation. • Chemical Deposition (deposition results from a chemical reaction) LPCVD, APCVD, PECVD, epitaxy, • Lithography • Removal • Wet isotropic etching • Wet anisotropic etching • Plasma etching • Reactive Ion Etching (RIE) • Deep Reactive Ion Etching (DRIE)

4. Photolithography • The technique of transferring the pattern on the mask to a layer of radiation sensitive material (resist) which, in turn, is used to transfer the pattern to the films or substrates through etching processes. • Masks patterns may be manually drawn on cut-and-peal masking films and photo reductions may be used in a fast turn-around device design research laboratory. • Modern masks consists of a patterned opaque chromium (the most common), emulsion, or iron oxide layer on a transparent fused-quartz or soda-lime glass substrate. • The pattern layout is generated using a computer-aided design (CAD) tool and transferred into the opaque layer at a specialized mask-making facility, often by electron-beam or laser-beam writing. • A complete microfabrication process normally involves several lithographic operations with different masks

5. Photolithography • Materials for substrates: • Silicon and quartz • Glass and ceramics • Materials for functional layers: • SiO2, Si3N4, poly-Si • Au, Cr, Cu, Al, Pyrex • Ni, NiFe, NiTi, ZnO • SU-8, BCB • The radiation used may be optical, X-ray, electron beam (e-beam), or ion beam • Optical exposure can be accomplished in one of three different modes: contact, proximity, or projection.

6. Exposure Methods • In contact lithography, the mask touches the wafer. This normally shortens the life of the mask and leaves undesired photoresist residue on the wafer and the mask. • In proximity mode, the mask is brought to within 25 to 50 µm of the resist surface. • In projection lithography projects an image of the mask onto the wafer through complex optics.

7. Minimum Resolvable Feature (Resolution) 2b: Minimum period transferable : Wave length of the exposing radiation s: Gap between photoresist and mask tR: Photoresist thickness Light Distribution Profile due to Fresnel diffraction

8. Minimum Resolvable Feature (Resolution) • Proximity Printing • = 400 nm, s>> tR • Contact Printing • = 400 nm, s=0, tR = 1µm (1µm) min. practical value (5µm) min. practical value

9. Minimum Resolvable Feature (Resolution) Projection Printing NA: Numerical aperture for the optics NA ~ 0.25 for typical MEMS stepper

10. Depth of Focus • Depth of focus (DOF) is a more severe constraint on lithography than resolution, especially in light of the need to expose thick resist or accommodate geometrical height variations across the wafer. • In contact lithography, and proximity modes, DOF is poor, limited by Fresnel diffraction. • In projection systems, the image plane can be moved by adjusting the focus settings, but once it is fixed, the depth of focus about that plane is limited to ±0.5×λ/NA2.

11. Photolithography Steps, Home Work #1 Removal of particulates, organic films, adsorbed metal ions Surface Cleaning Adhesion Promoter Sometimes used to achieve better adhesion of the resist Thickness varies with rotational speed of the spinner and viscosity of the resist Resist Application Prebake (Soft Bake) 70 °C – 90 ºC, necessary to drive solvent out of the resist Exposure Contact/proximity printing, projection printing Developing Negative resist: solvent; positive resist: alkaline developer 90 ºC – 140 ºC, necessary to increase both adherence and etch resistance Post Bake Etching/deposition/doping Stripping solutions, plasma etching in oxygene atmosphere Resist Removal

12. Surface Cleaning • Why is it important? • How is it done? • Physics/chemistry? • Parameters affecting it? Report + 10 min. PowerPoint presentation

13. Etching • Objective is to selectively remove material using imaged photoresist as a masking template. • The pattern can be etched directly into the silicon substrate or into a thin film, which may in turn be used as a mask for subsequent etches. • For a successful etch, there must be sufficient selectivity (etch-rate ratio) between the material being etched and the masking material. • Etch processes for MEMS fabrication deviate from traditional etch processes for the integrated circuit industry and remain to a large extent an art. • Deep etching of silicon lies at the core of bulk micromachining. No ideal silicon etch method exists, leaving process engineers with techniques suitable for some applications but not others. Distinctions are made on the basis of isotropy, etch medium, and selectivity of the etch to other materials.

14. Etching • Isotropic etchants etch uniformly in all directions, resulting in rounded cross sectional features. • Anisotropic etchants etch in some directions preferentially over others, resulting in trenches or cavities delineated by flat and well defined surfaces, which need not be perpendicular to the surface of the wafer. • Wet etchants in aqueous solution offer the advantage of low-cost batch fabrication. 25 to 50 100-mm-diameter wafers can be etched simultaneously—and can be either of the isotropic or anisotropic type. • Dry etching involves the use of reactant gases, usually in a low-pressure plasma, but nonplasma gas-phase etching is also used to a small degree. It can be isotropic or vertical. • The equipment for dry etching is specialized and requires the plumbing of ultra-clean pipes to bring high purity reactant gases into the vacuum chamber.

15. Isotropic Wet Etching • The most common group of silicon isotropic wet etchants is HNA, also known as iso etch and poly etch because of its use in the early days of the integrated circuit industry as an etchant for polysilicon. • It is a mixture of hydrofluoric (HF), nitric (HNO3), and acetic (CH3COOH) acids, although water may replace the acetic acid. • In the chemical reaction, the nitric acid oxidizes silicon, which is then etched by the hydrofluoric acid. • The etch rate of silicon can vary from 0.1 to over 100 µm/min depending on the proportion of the acids in the mixture. • Etch uniformity is normally difficult to control but is improved by stirring.

16. Anisotropic Wet Etching • Anisotropic wet etchants are also known as orientation-dependent etchants (ODEs) because their etch rates depend on the crystallographic direction. • Anisotropic wet etchants includes the hydroxides of alkali metals (e.g., NaOH, KOH, CsOH), simple and quaternary ammonium hydroxides (e.g., NH4OH, N(CH3)4OH), and ethylenediamine mixed with pyrochatechol (EDP) in water. The solutions are typically heated to 70º–100ºC. • Etch rate in {111} is much slower than other directions, which results in three-dimensional faceted structures formed by intersecting {111} planes with other crystallographic planes. This feature is routinely used to make V-shaped grooves and trenches in (100) silicon wafers, which are precisely delineated by {111} crystallographic planes. • The design of the masking pattern demands a visualization in three dimensions of the etch procession. To that end, etch computer simulation software, such as the program ACES™ available from the University of Illinois at Urbana-Champaign are useful design tools.

17. KOH Anisotropic Wet Etching • KOH is by far the most common ODE. Etch rates are typically given in the [100] direction, corresponding to the etch front being the (100) plane. • The {110} planes are etched in KOH about twice as rapidly as {100} planes, while {111} planes are etched at a rate about 100 times slower than for {100} planes. • The etch rate of KOH and other alkaline etchants also slows greatly for heavily doped p-type (p++) silicon due to the lower concentration of electrons needed for this etch reaction to proceed. P++ silicon is thus commonly used as an etch stop. • The etch rate of undoped or n-type silicon in KOH solutions is approximately 0.5 to 4 µm/min depending on the temperature and the concentration of KOH, but it drops by a factor of over 500 in p++ silicon with a dopant concentration above 1 × 1020cm−3. • LPCVD silicon nitride is an excellent masking material against etching in KOH. Silicon dioxide etches at about 10 nm/min and can be used as a masking layer for very short etches. Photoresist is rapidly etched in hot alkaline solutions and is therefore not suitable for masking these etchants.

18. KOH Anisotropic <100> Etching • The easiest structures to visualize are V-shaped cavities etched in (100)-oriented wafers. The etch front begins at the opening in the mask and proceeds in the <100> direction, which is the vertical direction in (100)-oriented substrates, creating a cavity with a flat bottom and slanted sides. The sides are {111} planes making a 54.7º angle with respect to the horizontal (100) surface. If left in the etchant long enough, the etch ultimately self-limits on four equivalent but intersecting {111} planes, forming an inverted pyramid or V-shaped trench. This occurs only if the wafer is thicker than the projected etch depth. • Timed etching from one side of the wafer is frequently used to form cavities or thin membranes. Hourglass and oblique-shaped ports are also possible in {100} wafers by etching aligned patterns from both sides of the wafer and allowing the two vertical etch fronts to coalesce and begin etching sideways, then stopping the etch after a predetermined time.

19. Concave and Convex Corners • While concave corners bounded by {111} planes remain intact during the etch, convex corners are immediately attacked. This is because any slight erosion of the convex corner exposes fast-etching planes especially {411} planes other than {111} planes, thus accelerating the etch. • A convex corner in the mask layout will be undercut during the etch; in other words, the etch front will proceed underneath the masking layer. • In some instances, such as when a square island is desired, this effect becomes detrimental and is compensated for by clever layout schemes called corner compensation. Often, however, the effect is intentionally used to form beams suspended over cavities.

20. KOH Anisotropic <110> Etching • In silicon (110) wafers, two of the four equivalent {111} planes are perpendicular to the (110) wafer surface. The remaining two {111} planes are slanted at 35.3º with respect to the surface. • The two vertical {111} planes intersect to form a parallelogram with an inside angle of 70.5º. • A groove etched in (110) wafers has the appearance of a complex polygon delineated by six {111} planes, four vertical and two slanted. • Etching in (110) wafers is useful to form trenches with vertical sidewalls, albeit not orthogonal to each other

21. Alignment Patterns and Etch Rates <110> wafer

22. Alignment Patterns and Etch Rates Lateral underetch rate as a function of orientation for 50% KOH solution at 78 oC <100> wafer <110> wafer

23. KOH Anisotropic Wet Etching • Alkali hydroxides are extremely corrosive; aluminum bond pads inadvertently exposed to KOH are quickly damaged. • CMOS fabrication facilities are very reluctant to use such etchants or even accept wafers that had previously been exposed to alkali hydroxides for fear of contamination of potassium or sodium, two ions detrimental to the operation of MOS transistors.

24. Electrochemical Etching • The relatively large etch rates of anisotropic wet etchants (>0.5 µm/min) make it difficult to achieve uniform and controlled etch depths. Some applications, such as bulk-micromachined pressure sensors, demand a thin (5- to 20-µm) silicon membrane with dimensional thickness control and uniformity of better than 0.2 µm, which is very difficult to achieve using timed etching. • Thickness control is obtained by using a precisely grown epitaxial layer and controlling the etch reaction with an externally applied electrical potential. This method is commonly referred as electrochemical etching (ECE). • An n-type epitaxial layer grown on a p-type wafer forms a p-n junction diode that allows electrical conduction only if the p-type side is at a voltage above the n-type; During ECE, the applied potential is such that the p-n diode is in reverse bias, and the n-type epitaxial layer is above its passivation potential—the potential at which a thin passivating silicon dioxide layer forms—hence, it is not etched. • The p-type substrate is allowed to electrically float, so it is etched. As soon as the p-type substrate is completely removed, the etch reaction comes to a halt at the junction, leaving a layer of n-type silicon with precise thickness.

25. Plasma Etching and Deep Reactive Ion Etching (DRIE) • Conventional plasma-phase etch processes are commonly used for etching polysilicon in surface micromachining and for the formation of shallow cavities in bulk micromachining. • The introduction in the mid 1990s of deep reactive ion etching (DRIE) systems provided a new powerful tool for the etching of very deep trenches (over 500 µm) with nearly vertical sidewalls. • Plasma etching involves the generation of chemically reactive neutrals (e.g., F, Cl), and ions (e.g., SFx +) that are accelerated under the effect of an electric field toward a target substrate. The reactive species (neutrals and ions) are formed by the collision of molecules in a reactant gas (e.g., SF6, CF4, Cl2, CClF3, NF3) with a cloud of energetic electrons excited by an RF electric field. • When the etch process is purely chemical, powered by the spontaneous reaction of neutrals with silicon, it is colloquially referred to as plasma etching. But if ion bombardment of the silicon surface plays a synergistic role in the chemical etch reaction, the process is then referred to as reactive ion etching (RIE). In RIE, ion (e.g., SFx +) motion toward the substrate is

26. Plasma Etching and Deep Reactive Ion Etching (DRIE) • When the etch process is purely chemical, powered by the spontaneous reaction of neutrals with silicon, it is colloquially referred to as plasma etching. But if ion bombardment of the silicon surface plays a synergistic role in the chemical etch reaction, the process is then referred to as reactive ion etching (RIE). In RIE, ion (e.g., SFx +) motion toward the substrate is nearly vertical, which gives RIE vertical anisotropy. • Asymmetric electrodes and low chamber pressures (5 Pa) are characteristic of RIE operation. Inductively coupled plasma reactive ion etching (ICP-RIE) provides greater excitation to the electron cloud by means of an externally applied RF electromagnetic field. Inductively coupled plasma (ICP) increases the density of ions and neutrals resulting in higher etch rates. • The ion bombardment energy is controlled by a separate power supply driving the platen on which the wafer sits.

27. Ion Milling • A different, purely physical method of etching is ion milling, in which noble-gas ions (usually argon) are remotely generated, then accelerated at the substrate though a potential on the order of 1 kV. The directionality of the ions results in a very vertical etch profile. • Because a chemical reaction is not required, any material can be etched by ion milling. The ion-milling rate is typically much slower than with RIE and varies widely with the material [4]