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APV25 I 2 C parameters

APV25 I 2 C parameters. Brief reminder of what the I2C registers do (from User Manual) Check on integration centre currently used parameters: TIB/TOB/TEC (thanks to Mariarosaria D’Alfonso, Andrea Rizzi, Katja Klein, Gaelle Boudoul) VPSP scan considerations

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APV25 I 2 C parameters

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  1. APV25 I2C parameters Brief reminder of what the I2C registers do (from User Manual) Check on integration centre currently used parameters: TIB/TOB/TEC (thanks to Mariarosaria D’Alfonso, Andrea Rizzi, Katja Klein, Gaelle Boudoul) VPSP scan considerations Some information from APV wafer test database on production uniformity e.g. how well will chips match without individual tuning Pointers to reference information m.raymond@imperial.ac.uk - July '06

  2. APV25 analog chain MUXGAIN VFP VFS VPSP IPSF ISSF IPSP IPRE IPCASC ISHA IMUXIN IPRE, IPCASC, IPSF, ISSF, IPSP, IMUXIN, ISHA currents provided by bias generator to set operating points of analogue stages 8 bit values 0 -> 255 (read/write register access) VFP, VFS, VPSP voltages generated by dumping programmable currents into on-chip resistors 8 bit values 0 -> 255 (read/write register access) ISHA and VFS are “free” parameters for tuning pulse shape, but can specify default values VPSP is “free” parameter for analogue baseline adjust – but watch power consumption (see later)

  3. APV mode register (R/W) 8 bit register – only 6 bits used bit no. 5 preamp polarity 0 = non-inverting 1 = inverting 4 readout frequency 0 = 20 MHz 1= 40 MHz 3 readout mode 0 = decon. 1 = peak 2 calibration inhibit 0 = OFF 1 = ON 1 trigger mode 0 = 3 sample 1 = 1 sample 0 analogue bias 0 = OFF 1 = ON examples: binary dec. 100101 37 inverting, 20 MHz, decon., cal inhibit ON, 3 sample, bias ON 101111 47 inverting, 20 MHz, peak, cal inhibit ON, 1 sample, bias ON 100001 33 inverting, 20 MHz, decon., cal inhibit OFF, 3 sample, bias ON 101011 43 inverting, 20 MHz, peak, cal inhibit OFF, 1 sample, bias ON normal operation no CAL normal operation with CAL

  4. MUX gain (R/W) 8 bit register – only 5 bits used feature included to accommodate extreme process variations in on-chip resistor values bit no. 4 highest 3 higher 2 nominal 0 = OFF 1 = ON 1 lower 0 lowest binary dec. 10000 16 +20% 01000 8 +10% 00100 4 nominal 00010 2 -10% 00001 1 -20%

  5. Calibration and Latency (R/W) Calibration - 8 bit registers CDRV mask (all ones except one you want to drive) e.g. 11101111 CSEL mask (all ones except delay you want to select – 8 steps of 3.125 nsec) there is a mistake in the user manual here! ICAL calibration pulse amplitude not well controlled – relies on small overlap region between two metal tracks so can use to “calibrate” (tune) pulse shape, but not gain Latency - 8 bit register sets separation between write and trigger pointers to the pipeline can take any value up to 191 if changed then must issue Reset101 to relaunch pipeline pointers otherwise chip will malfunction and latency error generated

  6. Error Register (Read only) • 8 bit register – only 2 bits used • bit 1 FIFO error (overflow – should not happen (APVE protects)) • bit 0 Latency error (distance between write and trigger pointers to pipeline • not equal to programmed latency) • can (should) only return: bin. dec. 00 0 no errors 01 1 latency error 10 2 FIFO error 11 3 latency and FIFO error SEU effects may well cause these errors if chip detects either error then error bit also set in output data header

  7. Integration centre parameters currently in use WARM (room temp. ~ +30) TIB TOB TEC+ TEC- IPRE 98 98 98 98 IPCASC 52 52 52 52 IPSF 34 34 34 34 ISHA 46 80 80 80 ISSF 34 34 34 34 IPSP 55 55 55 55 IMUXIN 34 34 34 34 ISPARE 0 0 0 0 ICAL 40 40 40 40 VFP 30 30 30 30 VFS 70 50 30 50 VPSP 37 34 37 33 CDRV 0 0 0 0 CSEL 8 8 8 8 MODE 47 37 47 37 LATENCY 100 100 100 100 MUXGAIN 4 4 4 4 ERROR 0 1 1 1 all subdetectors agree pulse shape and baseline adjustment “free” parameters needs to be set correctly for “calibration” (see p.5) preamp polarity / RO freq. / (decon/peak) / CAL inhibit / (3/1)sample / bias (ON/OFF) should be read only discrepancy may account for small differences observed in TEC+/TEC- performance?

  8. Parameters currently in use and proposed COLD (-10 -> -20) TIB TOB TEC IPRE 85 85 85 IPCASC 45 45 45 IPSF 30 30 30 ISHA 30 50 50 ISSF 30 30 30 IPSP 48 48 48 IMUXIN 30 30 30 ISPARE 0 0 0 ICAL 40 40 40 VFP 30 30 30 VFS 70 50 60 VPSP 37 - - CDRV 0 - - CSEL 8 - - MODE 47 - - LATENCY 100 100 100 MUXGAIN 4 4 4 ERROR 0 0 0 values used by TIB provided by Andrea Rizzi in agreement with: http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/cold_APV_params.pdf values for TOB/TEC are what I propose here in agreement with: http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TOB_cold_APV_params.pdf http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TEC_cold_APV_params.pdf all subdetectors agree pulse shape and baseline adjustment “free” parameters needs to be set correctly for “calibration” (see p.5) preamp polarity / RO freq. / (decon/peak) / CAL inhibit / (3/1)sample / bias (ON/OFF) should be read only

  9. Parameters currently in use and proposed WARM (room temp.) COLD (-10 -> -20) TIB TOB TEC+ TEC- TIB TOB TEC IPRE 98 98 98 98 85 85 85 IPCASC 52 52 52 52 45 45 45 IPSF 34 34 34 34 30 30 30 ISHA 46 80 80 80 30 50 50 ISSF 34 34 34 34 30 30 30 IPSP 55 55 55 55 48 48 48 IMUXIN 34 34 34 34 30 30 30 ISPARE 0 0 0 0 0 0 0 ICAL 40 40 40 40 40 40 40 VFP 30 30 30 30 30 30 30 VFS 70 50 30(50) 50 70 50 60 VPSP 37 34 37 33 37 - - CDRV 0 0 0 0 0 - - CSEL 8 8 8 8 8 - - MODE 47 37 47 37 47 - - LATENCY 100 100 100 100 100 100 100 MUXGAIN 4 4 4 4 4 4 4 ERROR 0 1 1 1 0 0 0 all subdetectors agree pulse shape and baseline adjustment “free” parameters needs to be set correctly for “calibration” (see p.5) preamp polarity / RO freq. / (decon/peak) / CAL inhibit / (3/1)sample / bias (ON/OFF) should be read only suggest default VFS (prior to tuning) -> 50 for TEC+ unless this causes problems for comparisons with previously measured data

  10. be careful with VPSP scans 100% VPSP setting adjusts analogue baseline position works by introducing DC voltage offset at APSP O/P which in turn produces DC offset current flowing in the MUX stages 50% analogue baseline 0 module power baseline pos’n TIB module measurement baseline setting has strong effect on overall power e.g. assume baseline tuned to ~ 25% relative to dig. head amp. get ~7% power increase if move from 25% to 50% level much more (~ 28%) if scan through full range for setting up, better to start with high value (low baseline) and scan down (baseline rises) until target value reached (then stop) see: http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/cold_APV_params.pdf http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/Detailed%20APV25%20Power%20Consumption.pdf

  11. Some info from APV production test data ~ 600 wafers (~ 216,000 chips) tested over ~ 4 years including early production wafers with yield problems which were not used production lots from lot 9 onwards individual chips subjected to detailed testing of analogue/digital functionality -> Known Good Die (KGD) individual chip results stored => analysis of database -> insight into overall uniformity note: I2C parameters used in production test kept constant throughout (including ISHA and VFS) except for VPSP Production wafer yields (360 chips / wafer)

  12. Normalised Pulse Shapes intensity plots show pulse shapes from all 131,734 KGD from 414 production wafers (lots 9 – 29) overlaid SPICE simulated peak mode pulse shapes show almost all chips lie within  1 s of nominal peak mode deconvolution => pulse shapes match quite well even without tuning

  13. Pulse shape tuning ISHA fixed, vary VFS VFS fixed, vary ISHA strong effect on peak pulse fall time weak effect strong effect on decon pulse shape weak effect

  14. Output Frame Parameters APV output frame consists of digital header followed by 128 analogue samples digital header amplitude set by on-chip current reference mean header amplitude and spread for all KGD/lot shows minimal lot dependence error bars show  1 std. dev. average analogue pedestal (baseline) set by VPSP – the only parameter varied during wafer test (tuned to position baseline at 25% of digital header range) mean value and spread of distributions of VPSP values required to set 25% level show some lot dependence, but well within available adjustment range peak mode deconvolution

  15. Reference information lots of info and links at: http://www.hep.ph.ic.ac.uk/~dmray/Tracker.html I2C parameter recommendations for different temperatures: http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/cold_APV_params.pdf http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TOB_cold_APV_params.pdf http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TEC_cold_APV_params.pdf APV production data analysis LECC paper: http://indico.cern.ch/getFile.py/access?contribId=108&resId=0&materialId=paper&confId=0510

  16. Transistor level – for info (1) preamp polarity select VFP VFS SHAPER INV pipeline PREAMP SF SF IPCASC IPSF ISHA ISSF IPRE

  17. Transistor level (2) APSP MUXGAIN VPSP IMUXIN IPSP

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