Team Morphing Architecture

1. Team Morphing Architecture Reconfigurable Computational Platform for Space

2. Objectives • The Reconfigurable Computational Platform project will deliver working hardware, which will demonstrate both appodization and image pixel correction. The hardware will consist of data path logic, memory units, an interconnect, and control logic. The Reconfigurable Computational Platform project serves as a step toward a full proof of concept that is required of the NASA funded FPPA chip design team.

3. Specifications • Two reconfigurable memory modules (RMMs). • Two reconfigurable processing modules (RPMs). • A reconfigurable interconnect, capable of passing data between the two RMMs and the two RPMs as needed. • A control unit capable of configuring the interconnect, RMMs, and RPMs for various memory access types. • Each RMM and RPM will have two control ports leading back to the control unit. • All data inputs and outputs pass through the interconnect. • 16 bit data paths. • Support for read and write modes in each RMM. • Support for dynamic FIFO, dynamic stack, linear, and RAM data access in each RMM. • Support asymmetric stack operations.

4. Constraints • Each RPM has already been designed, the RMMs must conform to their specifications. • No external control inputs. • Only data may pass through the interconnect. Control lines must be directly tied from the control unit to the RMMs and RPMs. • Each RMM must be capable of sending full/empty signals to each RPM. • Addressing must be handled internally by the RMMs, no control unit involvement is allowed. • RMMs must be addressable on 16k or 32k boundaries. • RMMs, RPMs, and the interconnect must be capable of a sustained transfer rate of 10Msamples/sec. • The design must be realizable in real, space safe hardware. • Power is a consideration; a low power design is preferred.

5. RCP Architecture

6. Control Unit • Get instructions from off chip • Switch operational modes in components • Set configurations in components • Assert write to memory in loading • Monitor memories for empty signals • Signal off chip for next value to load

7. Reconfigurable Memory Module • Two parts: • RAM Memory • Memory Controller • Generates addresses automatically • Sends and receives all data via Interconnect • Performs operations in response to signal from either Processing Node or the Control Unit

8. Reconfigurable Interconnect • Splits signals when needed • Connects RMM with PNs for each operation type

9. Processing Node • Computes operation • Send and receive data via the Interconnect • Handles all timing delays for data • Simulated with FPGA or similar device

10. Demonstration Applications • Appodization • Bad Pixel Replacement • Other Functional Requirements

11. Appodization

12. Highpass Filter • This step will be implemented utilizing one processing element and one reconfigurable memory module • RMM1 will hold interferogram data • RPM1 will implement highpass filter

13. Hamming Window • This step will be implemented utilizing one processing element and one reconfigurable memory module • RMM2 will hold the hamming window data • RPM2 will multiply the highpass signal with the hamming window

14. Bad Pixel Replacement • Spatial average will be implemented using both memory modules and one processing element • RMM1 will hold the image data • RPM1 will compute the average of each pixel using neighboring pixels and then choose to accept the current pixel or use the average • RMM2 will act as a buffer for corrected pixels

15. Other Functional Requirements • RMMS must support dynamic stack and FIFO operations

16. Parts Analysis • We will be using FPGAs and CPLDs to realize the interconnect, control unit, and both processing elements. • Actual rad-hard Honeywell SRAM chips will be used to realize our reconfigurable memory. • During testing phases, we will use unhardened SRAM with specifications similar to the Honeywell chips.

17. Honeywell SRAM Properties • Storage: 32Kx8 (32,768 bytes) • Physical Size: 0.630 +/- 0.007 • Read/Write Cycle time: <= 25ns • Power Consumption: 15mW • Single 5V +/- 10% power supply

18. Compatible Memory/Price List • Cypress CY7C198 - $9.04 • Cypress CY7C199 - $1.89 • Cypress CY7C199C - ~$2.00 • IDT 5962-8855206UA - $28.00 (Best!) • No software $ (using only Xilinx ISE and Moelsim)

19. PLD Price List • FPGAs range from $40 up to $100 • CPLDs range from $5 to $20 • Programming interfaces are < $10

20. Budget Breakdown • $1000 Maximum • $300 for various SRAM chips • ~$75 CPLDs (control unit, interconnect, reconfigurable memory control) • $250 for FPGAs • ~$30 for miscellaneous parts

21. Upcoming Milestones • Complete all block diagrams of sub components - December 10 • Start VHDL coding of components - December 13 • Order memory chips - December 13 • Possibly order FPGAs - December 17

22. Remaining Challenges • VHDL code for system architecture and all system sub components • VHDL simulations • Timing dependencies for all hardware devices • Building connections between all hardware components • Testing of hardware configurations • Testing of complete design in both hardware and software