ERD TWG Emerging Research Devices Telecon Meeting No. 6

1. ERD TWGEmerging Research DevicesTelecon Meeting No. 6 Jim Hutchby - Facilitating Thursday, February 26, 2009 9:00 am – 10:30 Eastern US Time ERD WG Telecon January 15, 2009 Pacific US Central US Eastern US Europe Taiwan Japan/Korea 6am 8am 9am 3pm 10pm 11pm

2. Complete discussion of the Logic Tables Discuss possibility that ERD/ERM Working Groups will conduct a process to select consensus Emerging Memory Technology Entries to highlight (similar to the process conducted last summer for Emerging Logic) Goal Scope Timeline Benchmarking Feb. 26, 2009 ERD Telecon Meeting Objectives

3. 5:00pm Check in & review meeting Hutchby Objectives/Agenda 5:05 Complete Logic Table Discussion Hiramoto-san proposed 3 Logic Tables & decide Bourianoff 5:20 Review request to highlight consensus Garner selected Emerging Memory Technology Entries 5:30 Discuss the process and timeline for Hutchby benchmarking and selecting consensus Garner Emerging Memory Technology Entries to highlight Goal Scope Timeline Benchmarking 6:30 Adjourn Meeting February26, 2009 ERD Telecon Meeting Agenda

4. Japan ERD-WG Feedback on Logic Tables Titles/Structure • Japan ERD WG made discussions on the Table 2 and Table 3 which were proposed in the teleconference on January 22. • Table 2: “Non-Conventional FET, Charge-based Extended CMOS Devices” • Table 3: “Non-FET, Non Charge-based ‘Beyond CMOS’ Devices • Our question was what "charge-based" means. In this definition, "charge-based" means that "the state variable is the charge" or "the information carrier is the charge"? If this is the "information carrier", we think this classification is very reasonable.

5. ERD ITWGEmerging Research DevicesWorking GroupProposal for Highlighting Promising Technology Options for Emerging Research Memory Devices Jim Hutchby & Mike Garner Wednesday March 18, 2009

6. Samsung, Hynix , and Micron proposed that the ERD/ERM identify memory technologies needing more focused support Proposal: ERD & ERM hold a workshop in October, ‘09 to review and assess emerging research memory devices Goal: Identify those emerging research memory technologies that need more focused research and resources Process: Same Process as the Logic Assessment in 2008 White paper prepared by Champions on each emerging research memory technology and circulated prior to the technology review and selection meetings Champions present Pros, Cons and research needed for technology Friendly critic presents balanced assessment ERD member summarizes inputs for ERD/ERM WGs Face to Face Presentations & Discussion Voting on Promising Technologies leading to consensus selection Identify Critical Research Needed Assessment of Promising Emerging Memory Devices

7. Straw Candidate Emerging Research Memory Technologies DRAFT No. 2 • FeFET Memory • Nanoelectromechanical Memory • Fuse/Anti-fuse Memory • Ionic Memory • Atomic Switch / Electrochemical Metal Memory • Molecular Memory • Mott Transition Memory • Ferroelectric Barrier Effects Memory

8. DRAFT GOAL With the goal of providing input to resource allocation decisions, ERD/ERM WGs will conduct an in-depth review and evaluation of specific pre-competitive emerging research memory devices to highlight the most promising device technologies for detailed roadmapping and accelerated research and development.

9. DRAFT SCOPE The scope of the review/evaluation of emerging research memory technologies will include only those device technologies which are in the pre-competitive research stage and are not in manufacturing development within any commercial organization. (Those technologies in manufacturing development by one or more companies are candidates for inclusion in PIDS/FEP.)

10. Production Ramp-up Model and Technology Cycle Timing 100M Research Development Production 200K 10M 20K Transfer to PIDS/FEP 1M 2K Volume (Parts/Month) Alpha Tool Beta Tool Production Tool 100K Volume (Wafers/Month) 200 10K 1st 2Cos. Reach Product 20 First Conf. Papers 1K 2 0 24 -96 -72 -24 -48 Months Source: 2009 ITRS – ERD/ERM/PIDS/FEP

11. Draft Timetable

14. BACKGROUND SLIDES

15. Develop/decide process, milestones, timeline Identify Major memory technology candidates Strong technical proponent and friendly critic teams and their leaders Knowledgeable ERD/ERM mentor for each proponent team Key questions to be addressed by the teams Background materials for each technical candidate Develop invitation to proponents & friendly critics Introduction Potential of technology – fundamental limits Barriers – Fundamental vs. technological/engineering Evaluation Criteria Definition of specific devices for roadmapping Readiness in 10-15 years Proposed ERD WG Process for Highlighting Candidate Technology Options for Emerging Memory Devices

16. Issue invitations to proponent and friendly critic team leaders and obtain their commitments Identify ERD/ERM Mentors – 1 per candidate memory technology Obtain a white paper & background materials from each candidate technology proponent team for ERD review ERD WG review candidate memory technologies using a formal process prior to FxF meeting to identify questions to be addressed in FxF meeting. Proposed ERD WG Process for Highlighting Candidate Technology Options for Emerging Memory Devices

17. Conduct a FxF review of categories with each proponent & friendly critic team making a presentation On second day of ERD FxF meeting, discuss/decide ERD’s prioritized recommendation of narrowed memory technology options. Mentors will lead the discussion of their candidate technology Write & submit report to the IRC on ERD WG’s recommendations Proposed ERD WG Process for Highlighting Candidate Technology Options for Emerging Memory Devices

18. Decision Making & Majority Voting Scheme Each member of ERD WG will be given a maximum of X votes to use in voting for their top X choices among the candidate technologies (Majority Voting scheme) ERD/ERM WG members present in the FIRST DAY Workshop & the SECOND DAY meeting will be eligible to vote at SECOND DAY meeting, based on their personal technical judgment, independent of their corporate affiliation or regional representation, Only 0 or 1 vote can be cast for any candidate technology Member does not have to use all X votes, but cannot use more than X votes. All members can participate in the straw vote. The Candidate Technologies will be ordered according to which received the largest number of votes. Consensus approval will be our goal, but a 75% affirmative vote will be required as a minimum. This is what is meant by the term approximate consensus.

19. 9:20 Review Process for selecting beyond CMOS emerging technologies 9:45 Discuss Technologies 9:45 NEMS Switch Technology 10:05 Spin Torque Transfer Technology 10:25 Carbon-based Nanoelectronics 10:45 Break 11:00 Atomic Switch / Electrochemical Metal Switch 11:20 Collective Spin Devices (including M-QCA) 11:40 Single Electron Transistors 12:00 CMOL and FPNI ERD “Beyond CMOS” Technology Selection MtgAgenda – SECOND DAY REDO THIS SLIDE

20. 12:50 Preliminary vote on technologies – Majority voting process 1:00 Discuss preliminary results 1:45 Second vote on technologies 2:00 Discuss the leading technologies resulting from vote 2:30 Final vote on the leading technology(ies) to determine if we have approximate consensus (75% of those voting) to recommend one or more for roadmapping and enhanced engineering development 2:45 Decide next steps in roadmapping the chosen technologies ERD “Beyond CMOS” Technology Selection Mtg Agenda – SECOND DAY (Cont’d) REDO THIS SLIDE