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VLSI Implementations of Threshold Logic

VLSI Implementations of Threshold Logic. Authors: V.I. Varshavsky , M.J. Avedillo , J.M. Quintana, A. Rueda , and E. Jimenez Presenter: Chen-Kuan Tsai 2012/03/23. Outline. β -driven Threshold Element ( β DTE) Basic Idea Proposed Structure Example: Full Adder Conclusion

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VLSI Implementations of Threshold Logic

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  1. VLSI Implementations of Threshold Logic Authors: V.I. Varshavsky, M.J. Avedillo, J.M. Quintana, A. Rueda, and E. Jimenez Presenter: Chen-Kuan Tsai 2012/03/23

  2. Outline • β-driven Threshold Element (βDTE) • Basic Idea • Proposed Structure • Example: Full Adder • Conclusion • Latch-type Threshold Logic (LCTL) Gate • Basic Structure • Working Principle • Example: 20-input AND/OR/Majority gates • Conclusion

  3. βDTE • Base for the idea • In (a), when both transistors are completely open, the output voltage is determined by the ratio below and by the thresholds the of transistors. • The proposed structure is based on output-wired invertors.

  4. βDTE • Basic idea • Ratio form of threshold function

  5. βDTE • Proposed structure • To provide that Vinvis a threshold function by selecting the inverter threshold appropriately and inversing the given function.

  6. βDTE • Example: Full Adder • Threshold representation of a full adder is where it follows that

  7. βDTE • Conclusion • A reduced structure contains twice less transistors per an input weight unit than the output-wired CMOS invertors. • When using βDTE instead of conventional CMOS gates, the increase in power consumption is the cost.

  8. LCTL • Basic structure • The threshold gate is based on the latch-type comparator with precharge and evaluation phases. • Comparator: M2/M5 and M7/M10 • Precharge/Evaluation phases: M1/M3 and M6/M8 • Inputs/Threshold: M4i and M9i

  9. LCTL • Working Principle • 1. Precharging occurs when VR is at a logic low, M1 and M6 are on, M3 and M8 are off, and both outputs are at a logic low.

  10. LCTL • Working Principle (cont.) • 2. Evaluation is depending on the current in the input path, either Iin > Iref or Iin < Iref. If Iin > Iref, OUT signal is at a logic high If Iin < Iref, OUT signal is at a logic low

  11. LCTL • Example: 20-input AND/OR/Majority gate Threshold gate U0 = [1, 1, …, 1; T], T=1, 10 or 20.

  12. LCTL • Conclusion • A generic low-power CMOS implementation is proposed for threshold gates.

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