Other Logic Implementations

1. Other Logic Implementations

2. Pass gate/Transmission Gate Pass Gate NMOS passes good logic ‘0’ PMOS passes good logic ‘1’ CMOS TRANSMISSION GATE (TG)

3. AND Gate

4. OR Gate

5. Multiplexer

6. EX-OR Gate

7. Delay Calculations of Pass gates

8. 4-1 MUX

9. High Current Delivery For High Current requirements of L-H transitions For High Current requirements of H-L transitions

10. Tristate

11. EX_OR

12. EX-OR/NOR With Driving Output

13. PLA

14. Example : PLA

15. Transistor level Implementation

16. Pseudo-nMOS Implementation Ground

17. Altera 40nm FPGA’ahttp://www.altera.com/literature/br/br-stratix-iv-hardcopy-iv.pdf Notes: • Y = I/O count, Z = package type (see the product catalog for more information) • ASIC gates calculated as 12 gates per logic element (LE), 5,000 gates per 18 x 18 multiplier(SRAMs, PLLs, test circuitry, I/O registers not included in gate count) • Not including MLABs

18. Sequential Circuits-Single Clock -ve going edge Single clock to synchronize operations Suitable for simple applications

19. FPGA Comparison Table

20. Sequential Circuits For correct operation, Solution: use a narrow clock pulse. (Impractical)

21. Clocking Conditions Condition to achieve proper operation: Problem: Clock Skew

22. Two-phase Non-Overlapping clocking Problems: • Routing two Clock Nets, • Lower Frequency of Operation

23. Different Latches Static latch with cross-coupled circuit Dynamic Static latch with clocked feedback Buffered static latch with clocked feedback

24. D-Latch and the Flip Flop Operations

25. The Master Slave Flip Flop +ve edge of CLK 2

26. Master Slave Flip Flop Setup time=G4+G5+G6 Hold time=G1+G2 W1=G5+G6+G3 W2=G9+G10+G7 Cycle time=W1+W2 • CLK generated locally • Typical arrangement,

27. CMOS two phase double latch circuits Dynamic Static un-buffered Static buffered

28. Edge Triggered, D Flip Flop NAND1 S Q NAND2 NAND5 clk R NAND3 NAND6 D NAND4 reset

29. When CLK changes from 0 to 1 Case1, D=0: tsetup= t4, thold=t3 NAND1 S Q NAND2 NAND5 clk R NAND3 NAND6 D NAND4 reset Path for hold Path for set up

30. NAND1 S Q NAND2 NAND5 clk R NAND3 NAND6 D NAND4 reset When CLK changes from 0 to 1 Case2, D=1 tsetup=t4 + t1 thold= t2 Path to set up Path to hold

31. NAND1 S Q NAND2 NAND5 clk R NAND3 NAND6 D NAND4 reset When CLK changes from 0 to 1 Case1, D=0: tsetup= t4, thold=t3 Case2, D=1 tsetup=t4 + t1 thold= t2

32. D Flip Flop Rising Edge Data Change

33. D Flip-Flop with direct set and clear

34. JK Flip-Flop

35. Thank you !