1 / 6

Disseny Electrònic Assistit per Ordinador

Disseny Electrònic Assistit per Ordinador. 2_FPGA_1 - 1. Dispositius lògics programables i VHDL. ispLSI1032E-. Estructura. HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers

colby
Download Presentation

Disseny Electrònic Assistit per Ordinador

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Disseny Electrònic Assistit per Ordinador 2_FPGA_1 - 1 Dispositius lògics programables i VHDL ispLSI1032E- Estructura HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Fast Random Logic — Security Cell Prevents Unauthorized Copying HIGH PERFORMANCE E 2 CMOS ® TECHNOLOGY — fmax = 90 MHz Maximum Operating Frequency — tpd = 12 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E 2 CMOS Technology — 100% Tested — 4mA output source

  2. Disseny Electrònic Assistit per Ordinador 2_FPGA_1 - 2 100 Ω 100 Ω 100 Ω 100 Ω RESET MODE SCLK ispEN 560pF 560pF 560pF 560pF Dispositius lògics programables i VHDL ispExpert- gravació CPLD 74HC367 ACK(10) SDOUT PAL GAL CPLD FPGA 100Ω DO0(2) SDIN 560pF DO1(3) DO2(4) Vcc http://www.latticesemi.com/products 10K DO3(5) Vcc DO6(8) 10K DO4(6) PAP.END(12) ERROR(15) Vcc GND(20) GND

  3. Disseny Electrònic Assistit per Ordinador 2_FPGA_1 - 3 Dispositius lògics programables i VHDL ispExpert- Assignació I/O Load Programe P+Verify P+Secure Pin Assignments Pin Name Pin Assignment Pin Type, Pin Attribute AD_L(6) 3 Bidirectional AD_L(4) 4 Bidirectional CB(0) 6 Input TRDY 9 Three-State Output RES 11 Input FRAME 13 Input AD_L(5) 16 Bidirectional CS_OUT 45 Output, PULLUP Schematic ABEL VHDL VERILOG EDIF (Altera) Fitxer .JED

  4. Disseny Electrònic Assistit per Ordinador 2_FPGA_1 - 4 AD_H(7) IN 10 AD_H(6) IN 71 AD_L(7) BIDI 60 AD_L(6) BIDI 3 CLK IN 66 FRAME IN 13 IRDY IN 72 RES IN 11 DEVSEL OUT 73 TRDY OUT 9 nom_fitxer.txt !!! Si "Constraint Manager" agafa el projecte previ a l'actual fer un "File" -> "Clean" Dispositius lògics programables i VHDL ispExpert- Assignació I/O

  5. Disseny Electrònic Assistit per Ordinador 2_FPGA_1 - 5 7 3 2 4 7 1 1 4 6 6 5 5 3 Dispositius lògics programables i VHDL ispExpert- Test-Bench New -> VHDL Test Bench Editar el VHDL (Test Bench) Veure tots els senyals del projecte: Signals -> Add to waveform -> Signals in design Functional Simulation Esborrar senyals si cal botó dret rata -> edit ->cut/delete all Options -> Simulation Options -> Default run length Run ..... Run

  6. Disseny Electrònic Assistit per Ordinador 2_FPGA_1 - 6 Dispositius lògics programables i VHDL VHDL- Test-Bench prova.vhd : programa principal LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY prova IS PORT ( a, b : IN std_logic; s : OUT STD_LOGIC); END; ARCHITECTURE arc OF prova IS BEGIN s <= a AND b; END arc; prova_tb.vhd : Test Bench LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY prova_tb IS END prova_tb; ARCHITECTURE arc OF prova_tb IS COMPONENT prova PORT ( a,b : IN std_logic; s: OUT STD_LOGIC); END COMPONENT; SIGNAL a,b,s : std_logic; BEGIN uu: prova PORT MAP ( a => a , b => b , s => s ); PROCESS BEGIN WAIT FOR 50 ms; a <= '1'; WAIT FOR 50 ms; a <= '0'; END PROCESS; b <= '0‘ , '1' AFTER 100 ms; END arc; a b 50ms

More Related