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3D-IC prototyping service at CMP

3D-IC prototyping service at CMP. Kholdoun TORKI Kholdoun.Torki@imag.fr CMP 46, Avenue Félix Viallet, 38031 Grenoble, France http://cmp.imag.fr. Agenda. Introduction Collaboration for 3D-IC MPW runs service Tezzaron Process overview 3D-IC Design Platform

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3D-IC prototyping service at CMP

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  1. 3D-IC prototyping service at CMP Kholdoun TORKI Kholdoun.Torki@imag.fr CMP 46, Avenue Félix Viallet, 38031 Grenoble, France http://cmp.imag.fr

  2. Agenda • Introduction • Collaboration for 3D-IC MPW runs service • Tezzaron Process overview • 3D-IC Design Platform • TSV and wafer stacking from austriamicrosystems • Conclusion

  3. Introduction • CMP created in 1981 • Offering industrial quality process lines (University process lines cannot offer a stable yield) • Design-kits to link CAD and MPW, to facilitate the design. • Customer base development • + Universities / Research Labs • + Industry • + 1000 Institutions in 70 countries • Non-profit, Non-sponsored

  4. Multi-Project Wafer (MPW) Multi-Project Wafer runs allow to share the price by sharing the reticle area. • Prototype fabrication. • Low volume productions (some hundreds to hundred thousands parts) • Prototypes • Low volume production Shared cost wafer

  5. Technology Process Portfolio in 2011 IC : austriamicrosystems 0.35 µ CMOS / CMOS-Opto 0.35 µ SiGe 0.35 µ HV CMOS 0.35 µ HV CMOS EEPROM 0.18 µ CMOS 0.18 µ HV CMOS STMicroelectronics 28nm/32nm CMOS 40nm CMOS 7LM 65nm CMOS 7LM 130nm CMOS 6LM 65nm SOI 130nm SOI 130nm SiGe BiCMOS 0.15 µ GaAs D-mode pHEMPT 0.18 µ CMOS TriQuintSemiconductor TowerJazz MEMS : 0.35 µ CMOS bulk micromachining CMP/austriamicrosystems 3D-IC : 2 Tiers 3D-IC / 130nm CMOS Tezzaron / GlobalFoundries PolyMUMPS MetalMUMPS SOI-MUMPS MEMSCAP

  6. CMC-CMP-MOSIS Collaboration

  7. Benefits for a global Infrastructure CMC / CMP / MOSIS partnering for 3D-IC process access • Stimulate the activity by sharing the expenses for manufacturing. • Join forces for the technical support, and dedicate roles for each partner. • Make easier the tech support for local users respectively by each local center. • Because there is no standard for the 3D-IC integration, it is urgent to setup an infrastructure making possible a broad adoption of 3D-ICs. That will have a beneficial effect on prices, more frequent MPW runs, and more skilled engineers.

  8. CMC-CMP-MOSIS partnering on 3D-IC CMP/CMC/MOSIS partner to introduce a 3D-IC process Grenoble, France, 22 June 2010, CMP/CMC/MOSIS are partnering to offer a 3D-IC MPW service based on Tezzaron’s SuperContact technology and GLOBALFOUNDRIES 130nm CMOS. The first MPW run is scheduled to 31 May 2011: - 2-tier face-to-face bonded wafers - 130nm CMOS process for both tiers - Top tier exposing TSV and backside metal pads for wire bonding. A design-kit supporting 3D-IC design with standard-cells and IO libraries is available. Further MPW runs will be scheduled supporting process flavors (multiple tiers beyond 2, different CMOS flavors for different tiers, ...) driven by user requirements. Potential users are encouraged to contact CMP for details : cmp@imag.fr

  9. CMC - CMP - MOSIS Cooperation • CMC supporting Canadian Customers • CMP supporting European Customers • MOSIS supporting US Customers

  10. Tezzaron 2-Tier Process (130nm CMOS) Process Overview

  11. Source Yole Development

  12. Tezzaron Process Flow for TSV and DBI (using Via Middle process) Starting wafer in 130nm (5 Cu metal layers + 6th Cu metal as DBI) Source Tezzaron

  13. Tezzaron Process Flow for TSV and DBI (using Via Middle process) Cu Cu Cu Cu Cu Cu Cu Cu Cu Cu Cu

  14. Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process) DBIs continuing the stacking Top Tier (10um thickness) Bottom Tier (Handle wafer) Source Tezzaron

  15. Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process) Bond pad for wire bonding or bump, flip-chip … Top Tier (10um thickness) Bottom Tier (Handle wafer) Source Tezzaron

  16. 3D-IC MPW runs

  17. 3D-IC MPW Initial Infrastructure First MPW Run organized by FermiLab using an Industrial Process Manufacturing Clustering HEP Labs 3D-IC Potential Users

  18. 3D Consortium : 1st MPW run MPW Full Frame Test chips: TX, TY 2.0 x 6.3 mm Notice Symmetry about vertical center line Subreticules: A, B, C, D, E, F, G, H, I, J 5.5 x 6.3 mm Top tiers Bottom Tiers Source FermiLab (3D Consortium Meeting)

  19. 3D-IC MPW Infrastructure CMC-CMP-MOSIS partnering to offer 3D-IC MPW runs Clustering Manufacturing In place 3D-IC Users In discussion In place Critical mass allow frequent MPW runs and low pricing

  20. CMP/MOSIS/CMC : 1st MPW run Deadline originally planned for May 31st, 2011

  21. 3D-IC Design Platform

  22. Tezzaron / GlobalFoundries Design Platform • The Design Platform ismodular. It has all features for full-custom design or semi-custom automaticgeneration design. • PDK : Original PDK from GF + (TSV / DBI) definition from Tezzaron • Libraries : CORE and IO standard libraries from ARM • Memory compilers : SPRAM, DPRAM and ROM from ARM • 3D-IC Utilities : Contributions developments embedded in the platform • Tutorials, User’s setup. • All modules inside the platform refer to a unique variable, making it portable to any site. The installation procedure is straightforward. • Support of CDB and OpenAccess databases.

  23. Collaborative Work to the Design Platform HEP labs contributing with Programs, Libraries, and Utilities. All included in the Design Platform • DBI (direct bonding interface) cells library. (FermiLab) • 3D Pad template compatible with the ARM IO lib. (IPHC) • Preprocessor for 3D LVS / Calibre (NCSU) • Skill program to generate an array of labels (IPHC) • Calibre 3D DRC (Univ. of Bonn) • Dummies filling generator under Assura (CMP) • Basic logic cells and IO pads (FermiLab) • Floor-planning / automatic Place & Route using DBIs, and TSVs (CMP) • Skill program generating automatically sealrings and scribes (FermiLab) • MicroMagic PDK (Tezzaron/NCSU)

  24. Virtuoso Layout Editor with 3D layers and verification Virtuoso from Cadence TSV Back Metal Calibre Back Pad Assura DBI

  25. True 3D Mask Layout Editor Technology Files fully supported by Tezzaron MicroMagic MAX-3D

  26. Automatic P & R Design Flow (From Floor-Plan to Routed Design) - Std cells Placement - Clock Tree Synthesis Filler Cells Placement - DBIs Placement - TSVs Placement - Obstructions on TSVs - Clock routing - Final routing

  27. PDK Tezzaron / GlobalFoundries chrt13lprf_DK009_Rev_1D (Version issued in Q1 2011) assura: FILLDRC LVS QRC assura calibre cds_cdb cds_oa doc eldo hercules hspice prep3DLVS skill spectre strmMaptables_ARM strmMaptables_Encounter calibre: 3DDRC 3DLVS DRC FILLDRC calibreSwitchDef hercules: DRC LVS STAR_RCXT

  28. NDA Edition Access to the Design-Rules and the Design Platform NDA Customer Request Signed NDA reception http://cmp.imag.fr Request to access from CMP Web page or by E-mail to : cmp@imag.fr The user receive by E-mail the NDA + ARM lirary Addendum. The user sign and return by post 2 original signed copies CMP forward to Tezzaron the NDAs. When Tezzaron is OK, they counter-sign and return one copy to CMP. CMP return the copy to the user and give the access to the DRM and Design-Platform. Foundry’s Agreement Yes Design kit & Design Rules access

  29. Users having access to the Design Platform Tezzaron Semiconductor, USA FermiLab, USA North Carolina State University, USA MOSIS, USA CMC Microsystems, Canada University of Sherbrooke, Canada + Other centers supported by MOSIS and CMC Not listed here. CPPM, Marseille, France IPHC, Strasbourg, France LAL, Orsay, France LPNHE, Paris, France IRFU, CEA Saclay, France LAPP, Annecy-Le-Vieux, France ENSTA PARISTECH, Paris, France ISEA, Toulouse, France ENSSAT – Universite Rennes, France CEA-DIF, France University of Bergamo, Italy University of Bologna, Italy University of Perugia, Italy INFN, Roma, Italy INFN, Pavia, Italy INFN, Pisa, Italy University of Bonn, Germany University of Barcelona, Spain IMSE-CNM-CSIC, Sevilla, Spain TuDelft, The Netherlands University of Turku, Finland Norwegian University, Trondheim, Norway 22 Users in Europe

  30. 100µ TSV on 0.35µ CMOS from Austriamicrosystems

  31. Conclusion • CMC-CMP-MOSIS collaboration to offer services for 3D-IC prototyping and low volume productions. • Continuous enhancements on the Design Platform offering updates, features, and design methodologies. • First MPW run deadline : May 31st, 2011

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