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The Monolithic 3D-IC

The Monolithic 3D-IC. A Disruptor to the Semiconductor Industry. 1. MonolithIC 3D  Inc. Patents Pending. Monolithic 3D Provides an Attractive Path to…. LOGIC. Monolithic 3D Integration with Ion-Cut Technology. Can be applied to many market segments. MEMORY. OPTO-ELECTRONICS.

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The Monolithic 3D-IC

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  1. The Monolithic 3D-IC A Disruptor to the Semiconductor Industry 1 MonolithIC 3D Inc. Patents Pending MonolithIC 3D Inc. Patents Pending

  2. Monolithic 3D Provides an Attractive Path to… LOGIC Monolithic 3D Integration with Ion-Cut Technology Can be applied to many market segments MEMORY OPTO-ELECTRONICS MonolithIC 3D Inc. Patents Pending • 3D-CMOS: Monolithic 3D Logic Technology • 3D-FPGA: Monolithic 3D Programmable Logic • 3D-GateArray: Monolithic 3D Gate Array • 3D-Repair: Yield recovery for high-density chips • 3D-DRAM: Monolithic 3D DRAM • 3D-RRAM: Monolithic 3D RRAM • 3D-Flash: Monolithic 3D Flash Memory • 3D-Imagers: Monolithic 3D Image Sensor • 3D-MicroDisplay: Monolithic 3D Display

  3. MonolithIC 3D Inc. Patents Pending FPGAs: The 3D-TSV Solution MonolithIC 3D Inc. Patents Pending

  4. Reinventing FPGA using 3D-TSV • Use different dies for: • Programmable Logic • Programmable I/O • Programmable Memory • Build Reticle Size with Multi-Dice Lines for each • ~One Mask set with many die/functions size options • Choice of process node and fabrication processes MonolithIC 3D Inc. Patents Pending

  5. FPGA chip with IO Scribe lanes IO “chiclet” with TSV prep Traditional wafer of chips TSVs FPGA Logic-only chunk TSV Continuous Array of Logic at 22nm Wafer of IO Chiclets at 0.15 m Traditional FPGA Wafers vs. Continuous Array Wafers Scribe lanes MonolithIC 3D Inc. Patents Pending

  6. Chip size 9 Chip size 4 Scribe lane Chip size 20 FPGA Logic-only chunk Continuous Array Terrain Allows Defining Custom Logic Sizes from Same Wafers • Long metal tracks cross scribe lines • Die edges need to be sealed after cut • Top wafer prepped for TSVs or micorbumps in standard pattern (“socket”) over logic chunks MonolithIC 3D Inc. Patents Pending

  7. Standard TSV pattern Chip with logic size 9 Chip with TSV visible 3D Hybrid stack with TSVs TSV prep • Chiclets assembly actually happens prior to wafer dicing IO 0.15 m memory 22 nm SerDes 90 nm Chiclets Assembling Continuous Array Terrain into Customized Hybrid Stacks MonolithIC 3D Inc. Patents Pending

  8. Advantages of 3D-TSV FPGA • Good Fit for the End User Application with optimal size of silicon - ~2-5 x cost reduction • Wide range of technologies and function • Reduce cost by using low cost old process for I/O • Increase functionality to match user alternative SC • Allow integration of additional vendors with their own dies • Huge reduction of $$$ for masks MonolithIC 3D Inc. Patents Pending

  9. Future SoC New Logic  15% MonolithIC 3D Inc. Patents Pending

  10. MonolithIC 3D Inc. Patents Pending FPGAs: The Monolithic 3D Solution MonolithIC 3D Inc. Patents Pending

  11. 3D IC Next Generation – Monolithic 3D Monolithic 3D vs. TSV(1:10,000vertical connectivity ratio) MonolithIC 3D Inc. Patents Pending

  12. Layer Transfer Technology (“Ion-Cut”) Defect-free single crystal formed @ <400oC Cleave using 400oC anneal or sideways mechanical force. CMP. Hydrogen implant of top layer Flip top layer and bond to bottom layer Oxide p- Si Top layer Oxide p- Si p- Si p- Si H Oxide Oxide Oxide Bottom layer Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today 12 MonolithIC 3D Inc. Patents Pending MonolithIC 3D Inc. Patents Pending

  13. Cleavable wafer ‘Smart Cut’ Thin crystalline silicon layer Oxide to oxide bonding High temp interconnect (tungsten) Isolation Transistors Programming Transistors Foundation – Pre-fabricated High Voltage Programming Transistors (‘Older’ Process) MonolithIC 3D Inc. Patents Pending

  14. Interconnect Antifuses House Programmable interconnect Crystalline Silicon Foundation Crystalline Silicon (base wafer) Primary Device (‘House’) on top of the Foundation MonolithIC 3D Inc. Patents Pending

  15. Vp- Vp- Vp- Vp+ Vp- Vp+ Vp+ Vp+ Vp+ Vp+ Vp+ Vp+ Vp+ Vp+ Vp+ Vp+ Vp+ Vp+ Vp+ Vp- Vp- Vp- Vp- Vp+ Vp- Vp- Vp- Vp- Vp- Vp- 3D Antifuse Connectivity ~ ASIC Connectivity M N M x N fully populated antifuse crossbar In the House . . House 3 . 2 . 1 3 2 1 Foundation M + N Programming transistors In the Foundation MonolithIC 3D Inc. Patents Pending

  16. Future Monolithic 3D FPGA • Multi-Tier Programmable Logic • Tier 0 – The LUT Array + Local programmable interconnect • Tier 1 – The Clock distribution Network + programmable power distribution • Tier 2 – Short Programmable Interconnect • Tier 3 – Long Programmable Interconnect • Reinvented PIC • Antifuse • 1T Memory cell instead of the 6T • Flash • DRAM • … MonolithIC 3D Inc. Patents Pending

  17. Summary • Interconnects are now dominating all logic devices • Early innovations of 3D FPGA stimulate more ideas • FPGA vendors are moving into 3D (so far 2.5D) • Future FPGAs will utilize 3D technology to Reinvent the FPGA • TSV to re-architect the FPGA system • Monolithic to re-architect the programmable logic fabric • The Future is in the Third Dimension – 3D MonolithIC 3D Inc. Patents Pending

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