1 / 22

Performance of the ABCN-25 readout chip for the ATLAS Inner Detector Upgrade

Performance of the ABCN-25 readout chip for the ATLAS Inner Detector Upgrade. Francis Anghinolfi CERN Wladyslaw Dabrowski AGH Krakow Nandor Dressnandt University of Pennsylvania Daniel La Marra University of Geneva Mitchell Newcomer University of Pennsylvania

danno
Download Presentation

Performance of the ABCN-25 readout chip for the ATLAS Inner Detector Upgrade

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Performance of the ABCN-25 readout chip for the ATLAS Inner Detector Upgrade Francis AnghinolfiCERN Wladyslaw Dabrowski AGH Krakow Nandor Dressnandt University of Pennsylvania Daniel La Marra University of Geneva Mitchell Newcomer University of Pennsylvania Pernecker Sebastien  University of Geneva Poltorak Karolina CERN Swientek Krzysztof AGH Krakow TWEPP09 F. Anghinolfi CERN/PH

  2. ABCN-25 : Silicon Strip Module/Stave Readout Concept • Outer Layers – long strips • 2 Layers R= 81.4, 95.4 cm • Granularity 12 cm x 80 um • Z length 2x190 cm • Middle Layers – short strips • 3 layers at R=38, 47.3, 57.4 cm • Granularity 3 cm x 80 um • Z length 2x100 cm Section of projected SI Tracker geometry (Nov.08) Disks Barrel SLHC ATLAS expected Tracker Occupancy (P. Nevski) Example of Barrel layout R. Nickerson, Oxford TWEPP09 F. Anghinolfi CERN/PH 2

  3. Module #1 Module #2 Module #12 Cooling In TTC, Data & DCS fibers Opto SC DCS interlock DCS env. IN Cooling Out SMC Hybrid Service bus PS cable ~1.2m MC MC MC MC MC MC ABCN-25 : Silicon Strip Module/Stave Readout Concept Cross section Sensor, Hybrid, ASIC Carbon Honeycomb Cooling Pipe ~ 1.2 meter TWEPP09 F. Anghinolfi CERN/PH 3

  4. ABCN25 : Module/Stave Readout Concept 10x10 cm2 Detector Segmented in 4 rows of 2.5cm strips Short strips module concept : 2 hybrids, each one reads 2 rows of 10 FE chips of 128 channels Detector has 4 rows of 1280 strips Per hybrid, data are daisy-chained from chip to chip up to the MC chip In case of 1 chip failure TWEPP09 F. Anghinolfi CERN/PH

  5. ABCN-25 Chip Description Digital part : reuse of existing SCT protocols, SEU protections, 80Mbits/sec output rate, power control , 2.3 mW/channel @2.5V 128 Channels Front-End opt. for Short Strips 0.7mW/channel ABCN 250nm is an intermediate version of the FE chip for stave/modules prototypes Serial regulator to provide analogue voltage from a unique digital+ analogue power source Shunt regulators (2 options) to exercise 2 different serial powering systems Design from Uni GE, Krakow, Penn University & CERN, reuse of cells of the ToTem VFAT2 chip TWEPP09 F. Anghinolfi CERN/PH 5

  6. ABCN-25 : Hybrid prototype Neighbouring ABCns wire bonded Inter-chip bonding 7.5mm 2.1mm 7.5mm Photos : courtesy Ashley Greenall Populated prototype hybrid with 20 ABCN-25 : Full functionality at 40 MHz BCO and 80MHz RO Analogue performance according to specs @ no detector Modules are built with segmented detectors (see A. Greenall poster in this TWEPP) Fully Populated Liverpool Hybrid TWEPP09 F. Anghinolfi CERN/PH 6

  7. Hybrid readout 40/40MHz SCTDAQ Data : A. Greenall Liverpool U. P. Phillips RAL ABCN-25 : Hybrid prototype Hybrid readout 40/80MHz • 105mV/fC gain at discri. input • 450el noise @ no detector • Threshold uniformity < 0.03fC • (after trimming) TWEPP09 F. Anghinolfi CERN/PH 7

  8. ABCN-25 : Specifications of the analogue Front-End FRONT-END SPECIFICATIONS TWEPP09 F. Anghinolfi CERN/PH 8

  9. ABCN-25 : Schematics of the analogue Front-End ABCN25 : Front End Circuit • Input transistor; NMOS 320um/0.5um, nominal bias 140uA • Nominal consumption 280uA @ 2.5V (2.2V after regulator) (0.7mW / channel@2.5v) • Peaking time 25ns (22ns intrinsic) • Time walk 1.25 – 10fC @ 1fC threshold ~15ns TWEPP09 F. Anghinolfi CERN/PH 9

  10. ABCN-25 Measurements Short strip • Input transistor; NMOS 320um/0.5um, nominal bias 140uA • Nominal consumption 280uA @ 2.5V (2.2V after regulator) (0.7mW / channel) TWEPP09 F. Anghinolfi CERN/PH 10

  11. ABCN-25 Measurements Gain NI-DAQ Data : M. Dwuznik, Krakow U., S. Gonzalez Sevilla, Geneva U. TWEPP09 F. Anghinolfi CERN/PH 11

  12. ABCN-25 Measurements Linearity 80 MHz readout 40 MHz readout NI-DAQ Data : M. Dwuznik, Krakow U., Sergio Gonzalez Sevilla, Geneva U. TWEPP09 F. Anghinolfi CERN/PH 12

  13. ABCN-25 Measurements Time Walk measurements Time walk measured for 1.25 to 10fC charge with 1fC discriminator threshold NI-DAQ Data : M. Dwuznik, Krakow U., Sergio Gonzalez Sevilla, Geneva U. TWEPP09 F. Anghinolfi CERN/PH 13

  14. ABCN-25 Digital Functions Digital Performance, Power Similar functionality and data format as ABCD, the readout chip of the present SCT detector but : Token mechanism btw. Chips modified to simplify hybrid routing Additional configuration commands, register read-back protocol added Radiation tolerant layout TMR on critical logic (Command decoder, configuration registers) 2 Shunt Devices to test 2 different Shunt mechanisms Design by : D. La Marra, S. Pernecker (Uni Geneva), W. Dabrowski, K. Swientek (Cracow University), N. Dressnandt, M. Newcomer (U. Penn), K. Poltorak, J. Kaplon, F. Anghinolfi (CERN) TWEPP09 F. Anghinolfi CERN/PH 14

  15. ABCN-25 digital current measurements Probably powered from other source (I/Os ?) Simple Digital tests OK at 1.3V (to be confirmed) The plot above shows that 48 mAare static current at 2.5V. 40MHz The dynamic current is 92 mAat 2.5V. 40MHz The current in the front-end is 35 mA at nominal biasing (not on this plot) TWEPP09 F. Anghinolfi CERN/PH 15

  16. ABCN-25 digital current measurements • activating a disable bit Digital Dynamic current @ 2.5V 40MHz SUM : ~40 % 60% of dynamic current (55 mA) for : input register, derandomizer, fast command decoder (triplicated), Data Compression Logic and Readout Logic. TWEPP09 F. Anghinolfi CERN/PH 16

  17. ABCN-25 Shunt Devices Shunt systems • Distributed Shunt, Internal Feedback Scheme • Use each ABCN’s integrated shunt regulator • Use each ABCN’s integrated power transistor(s) • Distributed Shunt, External Feedback Scheme • Use one external shunt regulator • Use each ABCN’s integrated power transistor(s) VDD 0.004 0.004 0.004 0.05 0.05 I1 I3 0.05 0.05 I0 I2 TEST conditions ABCN0 ABCN1 ABCN2 ABCN3 0.004 0.004 0.004 Return TWEPP09 F. Anghinolfi CERN/PH 17

  18. ABCN-25 Shunt Devices Shunt systems • Distributed Shunt, External Feedback Scheme • Use one external shunt regulator • Use each ABCN’s integrated power transistor(s) TWEPP09 F. Anghinolfi CERN/PH 18

  19. ABCN-25 Shunt Devices Shunt systems • Distributed Shunt, Internal Feedback Scheme • Use each ABCN’s integrated shunt regulator • Use each ABCN’s integrated power transistor(s) Ajustment and redistribution of the shunt current in case several devices connected in parallel Shunt current limiter Adjustment of the reference voltage TWEPP09 F. Anghinolfi CERN/PH 19

  20. ABCN-25 Shunt Devices Shunt systems • Distributed Shunt, Internal Feedback Scheme • Use each ABCN’s integrated shunt regulator • Use each ABCN’s integrated power transistor(s) TWEPP09 F. Anghinolfi CERN/PH 20

  21. ABCN : Further Developments For the next technology version we are considering : • To keep the same generic architecture as ABCD, ABCN25 : • Binary readout with L1 latency pipeline, L1 buffer, Data Compression Logic and Serialiser These features are under discussions : • New readout protocol • SEU detection/correction in chip • Number of channels per chip • Data coding (ECC, DC balancing, clock recovery) • On-chip power devices to adapt the DC-DC or SP powering schema • Slow Control functions TWEPP09 F. Anghinolfi CERN/PH

  22. ABCN : Further Developments There are many open options. However the present ABCN-25 is helping to test some options (like the powering schema) and to tune the future chips (ABCN and MC) specifications. This ASIC will be used for the build-up of the Modules and Stave Prototypes for the ATLAS Silicon Strips Upgrade (both Barrel and End-Cap) The power estimation/optimization is first priority for the ABCN-Next design (critical in the digital part) Power estimates for ABCN in 130nm technology, *powering and regulation overhead excluded TWEPP09 F. Anghinolfi CERN/PH

More Related