A Flexible Approach to High Level Simulation of Complex System-on-Chip

1. A Flexible Approach to High Level Simulation of Complex System-on-Chip Muhammad Usman Ilyas (LUMS, Pak) Syed Ali Khayam (MSU, USA) Muhammad Omer Suleman (Oxford, UK) Shahid Masud (LUMS, Pak)

2. Presentation Outline • Problem Definition • Traditional Simulation Techniques • Alternative Approach • Outline of Model • Implementation & Results • Conclusions

3. Problem Definition • Designs change very rapidly during the initial design phase. • The number of test vectors is very large. • Quick results are required.

4. Traditional Simulation Techniques • HDL-based simulations • Advantage: • Parallelism inherent to HDLs • Disadvantage: • Slow execution • Expense of software tools (Vendors: Synopsys, Cadence, Mentor Grpahics etc.) • Expense of hardware platforms (Sun)

5. Partial Workaround • HDL simulators allow independent modification of system and simulation clock resolutions. Assumptions -> Developers are not interested in timing issues at this stage • Max speedup is achieved by setting, resolution(simulation clock) = resolution(system clock)

6. Alternative Approach • Use sequential language for simulation • Advantages • Lower hardware cost (commodity intel machines, etc.) • Lower software cost (Linux flavors, MS OSs etc.) • Faster execution • Disadvantages • Sequential code execution (!) • Customized for each design (?)

7. Outline of Model • The model we propose has the following features • Implemented in a sequential language • Virtual parallel code execution • Cycle accurate • Mapping of system components to Bus Functional Models (BFM)

8. Model Characteristics • The state of the model changes only from one clock cycle to the next. Time is saved by not evaluating intermediate states.

9. Restrictions • Data exchanged between BFMs on clock transitions only. • A BFM may not consist entirely of combinational circuits

10. Module-to-BFM Mapping (1) • The process of mapping the modules of the design to BFMs depends on the level of abstraction. • BFMs mimicking modules at a high level of abstraction are best modeled as Finite State Machines (FSM) of variable complexity. • Glue Logic is modeled as simple logical equations.

11. Module-to-BFM Mapping (2) • Registers and memories are modeled as pairs of variables

12.  Incorrect Module-to-BFM Mapping

13. Corrected Module-to-BFM Mapping

14. Implementation (1) • This technique was applied during the initial design phase of the AVAZ VZM-1000 Media Processor targeted for use in VoIP gateways.

15. Implementation (2)

16. Results (1) • Language: C++ model • Compiler: MS Visual C++ 6 • OS: MS Windows 2000 Professional • Platform: intel P III, 733MHz, 256MB RAM Vs. • Language: Verilog • Compiler: VerilogXL • OS: Sun Solaris • Platform: Sun UltraSPARC Server, 2GB RAM

17. Results (2) • Code Complexity • Code complexity was measured by the number of code lines. • At equal levels of abstraction the code complexity of both Verilog and C++ codes was approximately the same. • Lower Execution Time • The C++ model performed approximately two orders of magnitudes faster. • Shorter Time-to-Market • Time-to-Market for this ASIC was reduced from approximately 18 months down to 10 months.

18. Verification App Screenshot

19. Verification App Screenshot

20. Conclusions • Performance wise, this simulation method has proven to be more time efficient. • The approach is more efficient in terms of tool & equipment cost. • The approach required a custom made simulation.

21. Acknowledgements • We were greatly facilitated in the work presented by, • Dr. Shoab Ahmed Khan CEO, AVAZ Networks • M. Mohsin Rahmatullah Manager (SoC), AVAZ Networks

22. References (1) [1] Keith Westgate and Don McInnis, “Cycle-based simulation”, http://www.quickturn.com/tech/cbs.htm on December 19th, 2002. [2] Patrick A. McCabe, “VHDL-based system simulation and performance measurement”, VHDL International Users’ Forum Meeting, May, 1994, Oakland, CA USA. [3] Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park and Chong-Min Kyung , “Virtual chip: Making functional models work on real target systems”, 35th ACM DAC98 , June, 1998, San Francisco, CA USA. [4] Luc Semeria, Andrew Seawright, Renu Mehra, Daniel Ng, Arjuna Ekanayake and Barry Pangrle, “RTL C-based methodology for designing and verifying a multi-threaded processor”, DAC 2002, June 10-14, 2002, New Orleans, Louisiana, USA.

23. References (2) [5] Moon Gyung Kim, Byung In Moon, Sang Jun An, Dong Ryul Ryu, and Yong Surk Lee, “Implementation of a cycle-based simulator for the design of a processor core”, IEEE Asia-Pacific ASIC conference (AP-ASIC), 1999. [6] Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park and Chong-Min Kyung, “Virtual Chip: Making Functional Models Work On Real Target Systems”, 35th ACM DAC98, June, 1998, San Francisco, CA USA. [7] H. Al-Asaad, D. Van Campenhout, J. P. Hayes, T. Mudge and R. B. Brown, “High-level design verification of microprocessors via error modeling”, Proceecdings IEEE International Workshop on High Level Design Validation and Test, Nov. 1997, pp. 194-201. [8] Yufeng Luo, Tjahjadi Wongsonegoro and Adnan Aziz, “Hybrid Techniques for Fast Functional Simulation”, 35th ACM DAC98, June, 1998, San Francisco, CA USA.

24. Thank You Q & A